IP Library Granted Patent US 9,418,734
Granted Patent B2
US 9,418,734 · App. 14/456,510 · Granted Aug 16, 2016

Multi-function resistance change memory cells and apparatuses including the same

Inventor: Scott E. Sills (Boise, ID)
Assignee: Micron Technology, Inc.
G11C13/0023G11C11/005G11C11/5685G11C13/0002G11C13/0011G11C13/0033G11C13/0069G11C14/00G11C2013/0078G11C2013/0083G11C2013/0092
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Quick Facts
Patent No.
US 9,418,734
App. No.
14/456,510
Granted
Aug 16, 2016
Kind
B2
Abstract

Various embodiments comprise apparatuses including drive circuitry to provide signal pulses of a selected time duration and/or amplitude to a number of memory cells. The memory cells may include an array of resistance change memory cells to be electrically coupled to the drive circuitry. The resistance change memory cells may be programmed for a range of retention time periods and operating speeds based on the received signal pulse. Additional apparatuses and methods are described.

Claims (34)

1. An apparatus comprising a plurality of resistance change memory (RCM) cells, the apparatus comprising:

a first region of the RCM cells;

a second region of the RCM cells; and

drive circuitry to selectively provide one of a plurality of signal pulse types to the first region of the RCM cells and to selectively provide a different one of the plurality of signal pulse types to the second region of the RCM cells, each of the plurality of signal pulse types having a different attribute and corresponding to a different memory function type, at least one of the plurality of signal pulse types being configurable in both amplitude and time duration to vary a data retention time of at least one of the RCM cells by controlling at least one of a height parameter and a radial growth parameter of a localized conduction region of the at least one RCM cell.

2. The apparatus of claim 1 , wherein the plurality of signal pulse types comprises a plurality of programming pulse types.

3. The apparatus of claim 1 , wherein the attribute comprises an integration of the pulse amplitude and the pulse time duration.

4. An apparatus, comprising:

a plurality of resistance change memory (RCM) cells each having a localized conduction region, the plurality of RCM cells including

a first region of the RCM cells;

a second region of the RCM cells; and

drive circuitry to selectively provide one of a plurality of signal pulse types to the first region of the RCM cells and to selectively provide a different one of the plurality of signal pulse types to the second region of the RCM cells, the plurality of signal pulse types to control both a height parameter and a radial growth parameter of the localized conduction region of selected ones of the RCM cells.

5. The apparatus of claim 4 , wherein each of the plurality of signal pulse types has a different attribute and corresponds to a different one of a plurality of memory function types.

6. The apparatus of claim 5 , wherein the plurality of memory function types include volatile memory, storage class memory, and one-time programmable memory.

7. The apparatus of claim 4 , wherein the plurality of signal types are configurable in both amplitude and time duration to vary a data retention time of the selected ones of the RCM cell.

8. The apparatus of claim 4 , wherein the plurality of RCM cells are conductive-bridging random access memory (CBRAM) cells.

9. The apparatus of claim 4 , wherein the plurality of RCM cells and the drive circuitry are formed on a single integrated circuit die.

10. An apparatus, comprising drive circuitry to selectively provide one of a plurality of signal pulse types to a first region of a plurality of resistance change memory (RCM) cells and to selectively provide a different one of the plurality of signal pulse types to a second region of the plurality of RCM cells, each of the plurality of signal pulse types having a different attribute and corresponding to one of a plurality of different memory function types including volatile memory, storage class memory, and one-time programmable memory.

11. An apparatus, comprising:

a plurality of memory regions each including a respective plurality of resistance change memory (RCM) cells, the respective plurality of RCM cells being based on electrochemical deposition of metal ions within an electrolyte;

control and select circuitry to determine a memory function type to emulate for information to be stored in selected ones of the plurality of memory regions, the apparatus and to select one of the plurality of memory regions to store the information; and

drive circuitry to provide to the selected one of the plurality of memory regions a pulse configured to emulate the determined memory function type for the information.

12. The apparatus of claim 11 , wherein the memory function type includes at least one of the group comprising volatile memory, storage class memory, and one-time programmable memory.

13. A method, comprising:

determining one of a plurality of memory function types to emulate; and

applying a programming pulse, having an attribute configured to emulate the determined memory function type, to one or more selected ones of a plurality of resistance change memory (RCM) cells, the attribute comprising an integration of at least one pulse amplitude having a pulse time duration associated with each of the at least one pulse amplitudes, the RCM cells being based on a voltage-driven ionic migration and electrochemical deposition of metal ions within an electrolyte.

14. The method of claim 13 , further comprising:

applying a first energy pulse to a first selected one of the plurality of RCM cells to form a lower value of conductance in a localized conduction region of the first selected RCM cell to retain an associated resistance state for a short duration; and

applying a second energy pulse having a higher energy than the first energy pulse to a second selected one of the plurality of RCM cells to form a higher value of conductance, relative to the lower value of conductance, in the localized conduction region of the second selected RCM cell to retain an associated resistance state for a longer duration, relative to the short duration.

15. The method of claim 14 , wherein, subsequent to applying the first energy pulse, applying one or more additional ones of the first energy pulse to refresh the lower value of conductance in the localized conduction region of the first selected RCM cell.

16. The method of claim 13 , further comprising increasing a voltage of the applied programming pulse to increase both a height and a radial growth of the one or more selected ones of the RCM cells to increase programming speed of the selected RCM cell.

17. The method of claim 13 , wherein each applied programming pulse is applied as a plurality of separate signal pulses.

18. The method of claim 13 , further comprising selecting an amount of power applied in the programming pulse to the one or more selected ones of the RCM cells based on a retention time period selected for a predetermined data retention period.

19. The method of claim 13 , further comprising interpreting flag bits received from an external controller as an indication of what type of memory function is indicated for received data, the memory function being selected from a group including volatile memory, storage class memory, and one-time programmable memory.

20. A memory apparatus, comprising drive circuitry to electrically couple to a resistance change memory (RCM) cell to provide a signal pulse, the signal pulse being configurable in both amplitude and time duration to vary a data retention time of the RCM cell by controlling both a height parameter and a radial growth parameter of a localized conduction region of the RCM cell.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Continuation 13428944 · Mar 23, 2012
Related Publication 20140347914A1 · Nov 27, 2014