Apparatus and methods to provide power management for memory devices
View Patent ↗An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.
1. An apparatus comprising:
a first operational amplifier having a non-inverting input, an inverting input, and an output, wherein the non-inverting input is configured to receive a first reference voltage;
a first N-type insulated-gate field effect transistor (IGFET) having a gate, a drain, and a source, wherein the gate of the first N-type IGFET is coupled to the output of the first operational amplifier;
a first voltage divider having a first end, a second end, and at least one tap, wherein the first end is coupled to the source of the first N-type IGFET and the at least one tap is coupled to the inverting input of the first operational amplifier;
a first buffer amplifier having an input and an output, wherein the input is coupled to the gate of the first N-type IGFET;
a second buffer amplifier having an input and an output, wherein the input is coupled to the source of the first N-type IGFET;
a second N-type IGFET having a gate, a drain, and a source, wherein the gate of the second N-type IGFET is operatively coupled to the output of the first buffer amplifier in a first mode; and
a P-type IGFET having a gate, a drain, and a source, wherein the gate of the P-type IGFET is operatively coupled to the output of the second buffer amplifier in the first mode, wherein the source of the P-type IGFET is coupled to the source of the second N-type IGFET and to an output node, wherein the output node is configured to provide a bias for a memory access line.
2. The apparatus of claim 1 , further comprising a capacitor having an end coupled to the gate of the second N-type IGFET.
3. The apparatus of claim 1 , wherein the voltage divider comprises a plurality of taps of different voltage levels, wherein the at least one tap is selected from the plurality of taps during production.
4. The apparatus of claim 1 , wherein at least one resistor of the voltage divider is laser trimmed during production.
5. The apparatus of claim 1 , further comprising an enable switch coupled to a drain of the first N-type IGFET.
6. The apparatus of claim 1 , further comprising:
a second operational amplifier having a non-inverting input, an inverting input, and an output, wherein the non-inverting input is configured to receive a second reference voltage;
a third N-type IGFET having a gate, a drain, and a source, wherein the gate of the third N-type IGFET is coupled to the output of the second operational amplifier;
a second voltage divider having a first end, a second end, and at least one tap, wherein the first end is coupled to the source of the third N-type IGFET and the at least one tap is coupled to the inverting input of the second operational amplifier;
a third buffer amplifier having an input and an output, wherein the input is coupled to the gate of the third N-type IGFET; and
a fourth buffer amplifier having an input and an output, wherein the input is coupled to the source of the third N-type IGFET;
wherein the gate of the second N-type IGFET is operatively coupled to the output of the third buffer amplifier in a second mode;
wherein the gate of the P-type IGFET is operatively coupled to the output of the fourth buffer amplifier in the second mode.
7. The apparatus of claim 6 , further comprising:
for the first mode, closing a first switch and a second switch and opening a third switch and a fourth switch; and
for the second mode, opening the first switch and the second switch and closing the third switch and the fourth switch;
wherein the first switch is disposed in a signal path between an output of a first buffer amplifier that generates the first buffered voltage and the gate of the second N-type IGFET;
wherein the second switch is disposed in a signal path between an output of a second buffer amplifier that generates the second buffered voltage and the gate of the P-type IGFET;
wherein the third switch is disposed in a signal path between an output of a third buffer amplifier that generates the third buffered voltage and the gate of the second N-type IGFET; and
wherein the fourth switch is disposed in a signal path between an output of a fourth buffer amplifier that generates the fourth buffered voltage and the gate of the P-type IGFET.
8. The apparatus of claim 6 , further comprising:
a first switch disposed in a signal path between the output of the first buffer amplifier and the gate of the second N-type IGFET;
a second switch disposed in a signal path between the output of the second buffer amplifier and the gate of the P-type IGFET;
a third switch disposed in a signal path between the output of the third buffer amplifier and the gate of the second N-type IGFET; and
a fourth switch disposed in a signal path between the output of the fourth buffer amplifier and the gate of the P-type IGFET.
9. A method of generating a bias for a memory access line at an output node, the method comprising:
receiving a first reference voltage at a non-inverting input of a first operational amplifier;
biasing a gate of a first N-type insulated-gate field effect transistor (IGFET) via an output of the first operational amplifier;
generating a first divided voltage by dividing a source voltage of the first N-type IGFET, and providing the first divided voltage to an inverting input of the first operational amplifier;
buffering a gate voltage of the first N-type IGFET to generate a first buffered voltage;
buffering a source voltage of the first N-type IGFET to generate a second buffered voltage;
in a first mode, source following the first buffered voltage with a second N-type IGFET, wherein a source of the second N-type IGFET is operatively coupled to an output node; and
in the first mode, source following the second buffered voltage with a P-type IGFET, wherein the source of the P-type IGFET is also coupled to the output node.
10. The method of claim 9 , further comprising storing a voltage of a gate of the second N-type IGFET with a capacitor.
11. The method of claim 9 , further comprising selecting the first divided voltage by selecting a tap from a plurality of taps of a voltage divider.
12. The method of claim 9 , further comprising laser trimming at least one resistor of a voltage divider during production, wherein the voltage divider generates the first divided voltage.
13. The method of claim 9 , further controlling enabling and disabling of the first N-type IGFET via an enable switch coupled to a drain of the first N-type IGFET.
14. The method of claim 9 , further comprising:
receiving a second reference voltage at a non-inverting input of a second operational amplifier;
biasing a gate of a third N-type IGFET via an output of the second operational amplifier;
generating a second divided voltage by dividing a source voltage of the third N-type IGFET, and providing the second divided voltage to an inverting input of the second operational amplifier;
buffering a gate voltage of the third N-type IGFET to generate a third buffered voltage; and
buffering a source voltage of the third N-type IGFET to generate a fourth buffered voltage;
in a second mode, source following the third buffered voltage with the second N-type IGFET;
in the second mode, source following the fourth buffered voltage with the P-type IGFET.