SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

1 . A semiconductor memory device, comprising:

a nonvolatile memory cell; and

a control circuit that performs write control on the memory cell,

the control circuit executing:

a first write operation that performs a write on the memory cell using a first write voltage;

a first verify operation that determines whether a threshold voltage of the memory cell exceeds a first threshold value due to the first write operation, or not;

a second verify operation that re-determines on the memory cell that has passed the first verify operation whether the threshold voltage exceeds the first threshold value, or not; and

a second write operation that performs a write on the memory cell that has not passed the second verify operation, using a second write voltage.

2 . The semiconductor memory device according to claim 1 , wherein

the first write voltage increases stepwise.

3 . The semiconductor memory device according to claim 2 , wherein

the second write voltage is equal to the first write voltage when the first verify operation has been passed.

4 . The semiconductor memory device according to claim 1 , wherein

the memory cells are arranged in series, sandwiched by a plurality of select transistors, in a region of intersection of a word line and a bit line.

5 . The semiconductor memory device according to claim 4 , wherein

the control circuit increases the first write voltage in the first write operation by increasing stepwise a voltage applied to the word line according to a result of the first verify operation.

6 . The semiconductor memory device according to claim 5 , wherein

in the second write operation, the control circuit applies to the bit line a voltage corresponding to an amount of increase of an applied voltage in the word line.

7 . The semiconductor memory device according to claim 4 , wherein at least one of the word line or the bit line extends vertical to the surface of a substrate in which the nonvolatile memory cell is provided.

8 . The semiconductor memory device according to claim 4 , wherein

the memory cells are arranged in a vertical direction with respect to a substrate to form a memory string connected to the bit line via the select transistor,

the memory string comprising:

semiconductor layers having columnar portion extending in a vertical direction with respect to the substrate;

a charge storage layer formed to surround the side surfaces of the columnar portions; and

conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer,

the conductive layers functioning as the word lines and as gate electrodes of the memory cells.

9 . A semiconductor memory device, comprising:

a nonvolatile memory cell; and

a control circuit that performs write control on the memory cell,

the control circuit executing:

a first write operation that performs a write on the memory cell using a first write voltage;

a first verify operation that determines whether a threshold voltage of the memory cell exceeds a first threshold value due to the first write operation, or not;

a second verify operation that determines whether the threshold voltage of the memory cell exceeds a second threshold value larger than the first threshold value due to the first write operation, or not;

a second write operation that performs a write on the memory cell that has passed the first verify operation and has not passed the second verify operation, using a second write voltage smaller than the first write voltage;

a third verify operation that re-determines on the memory cell that has passed the second verify operation whether the threshold voltage exceeds the second threshold value, or not; and

a third write operation that performs a write on the memory cell that has not passed the third verify operation, using a third write voltage.

10 . The semiconductor memory device according to claim 9 , wherein

the first write voltage and the second write voltage increase stepwise.

11 . The semiconductor memory device according to claim 10 , wherein

the third write voltage is equal to the second write voltage when the second verify operation has been passed.

12 . The semiconductor memory device according to claim 9 , wherein

the memory cells are arranged in series, sandwiched by a plurality of select transistors, in a region of intersection of a word line and a bit line.

13 . The semiconductor memory device according to claim 10 , wherein

the control circuit increases the first write voltage in the first write operation by increasing stepwise a voltage applied to the word line according to a result of the first verify operation.

14 . The semiconductor memory device according to claim 13 , wherein

in the second write operation, the control circuit applies the second voltage to the memory cell by applying to the bit line a certain voltage larger than that applied to the bit line during the first write operation.

15 . The semiconductor memory device according to claim 14 , wherein

in the third write operation, the control circuit applies to the bit line a voltage that corresponds to a total of a voltage corresponding to an amount of increase of an applied voltage in the word line and the certain voltage in the second write operation.

16 . A method of controlling a semiconductor memory device, the semiconductor memory device comprising a nonvolatile memory cell, the method comprising:

performing a first write that performs a write on the memory cell using a first write voltage;

performing a first verify that determines whether a threshold voltage of the memory cell exceeds a first threshold value due to the first write step, or not;

performing a second verify that re-determines on the memory cell that has passed the first verify step whether the threshold voltage exceeds the first threshold value, or not; and

performing a second write that performs a write on the memory cell that has not passed the second verify step, using a second write voltage.