Integration of semiconductor memory cells and logic cells
A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing.
1. A method for manufacturing a semiconductor device having a memory cell area and a logic cell area, comprising:
preparing a silicon substrate;
forming a polysilicon gate electrode in the memory cell area;
forming a dummy polysilicon gate electrode in the logic cell area;
removing the dummy polysilicon gate electrode from the logic cell area;
forming a gate insulation film and a metal gate electrode having a recess portion, in place of the removed dummy polysilicon gate electrode;
forming contact holes on source regions and drain regions of the memory cell area and the logic cell area;
filling the recess portion of the metal gate electrode and the contact holes concurrently with a wiring metal; and
planarizing the wiring metal by polishing.
2. The method of claim 1 , wherein the removing the dummy polysilicon gate electrode comprises exposing the gate top surfaces of the dummy polysilicon gate electrode by etching.
3. The method of claim 1 , wherein the memory cell area comprises a plurality of flash memory cells.
4. The method of claim 1 , wherein the logic cell area comprises a plurality of negative-channel metal-oxide-semiconductor field-effect transistors (NMOSFET).
5. The method of claim 1 , wherein the logic cell area comprises a plurality of positive-channel metal-oxide-semiconductor field-effect transistors (PMOSFET).
6. The method of claim 1 , wherein the forming the gate insulation film and the metal gate electrode comprises utilizing at least one of a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or a physical vapor deposition (PVD) method.
7. The method of claim 1 , wherein the gate insulation film comprises a thickness less than approximately 3 nm.
8. The method of claim 1 , wherein the metal gate electrode comprises a thickness less than approximately 5 nm.
9. The method of claim 1 , further comprising:
depositing a barrier metal film.
10. The method of claim 9 , wherein the depositing the barrier film is performed prior to the filling the recess portion of the metal gate electrode and the contact holes with the wiring metal.
11. The method of claim 1 , wherein the planarizing the wiring metal causes a top surface of the metal gate electrode to be higher than a top surface of the polysilicon gate electrode.