IP Library Granted Patent US 9,281,478
Granted Patent B2
US 9,281,478 · App. 14/458,804 · Granted Mar 8, 2016

Phase change memory cell with constriction structure

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,281,478
App. No.
14/458,804
Granted
Mar 8, 2016
Kind
B2
Abstract

Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Claims (19)

1. A device comprising:

a first electrode and a second electrode; and

a memory element directly contacting the first and second electrodes, the memory element including a programmable portion having a material configured to change between multiple phases, wherein the programmable portion is isolated from the first electrode by a first portion of the memory element, the programmable portion is isolated from the second electrode by a second portion of the memory element, each of the first and second portion having a material, the material of the first portion directly contacting the first electrode, the material of the second portion directly contacting the second electrode the memory element including an intermediate material between the first and second portions, the intermediate material being different from the material of each of the first portion, the second portion, and the programmable portion, and the intermediate material isolating the first portion from the second portion.

2. The device of claim 1 , wherein the memory element is configured to cause the material of the programmable portion to have a first phase of the multiple phases and to cause the material of each of the first and second portions to have a second phase of the multiple phases.

3. The device of claim 2 , wherein the material of programmable portion and the material at each of the first and second portion include chalcogenide material.

4. The device of claim 1 , wherein the material of the programmable portion has an amorphous phase, and the material of each of the first and second portion has a crystalline phase.

5. The device of claim 1 , wherein at least one of the first and second portions includes a tapered part, and the programmable portion include at least a part of the tapered part.

6. The device of claim 1 , wherein the intermediate material is different from a material of each of the first portion, the second portion, and the programmable portion.

7. The device of claim 1 , wherein the intermediate material has a resistance value lower than a resistance value of each of the first and second portions.

8. The device of claim 1 , wherein the first portion, the second portion, and the programmable portion include a same material.

9. The device of claim 1 , wherein the memory element includes a compound of germanium, antimony, and tellurium.

10. The device of claim 1 , wherein the memory element includes an intermediate material between the first and second portions.

11. The device of claim 10 , wherein the intermediate material includes one of TiN, ZrN, HfN, VN, NbN, TaN, TiC, ZrC, HfC, VC, NbC, TaC,TiB 2 , ZrB 2 , HfB 2 , VB 2 , NbB 2 , TaB 2 , Cr 3 C 2 , Mo 2 C, WC, CrB 2 , Mo 2 B5, W 2 B 5 , TiA1N, TiSiN, TiW, TaSiN, TiCN, SiC, B 4 C, WSix, MoSi 2 , NiCr, doped silicon, carbon, platinum, niobium, tungsten, and molybdenum.

12. A method comprising:

forming a first electrode and a second electrode of a device; and

forming a memory element directly contacting the first and second electrodes, the memory element including a programmable portion having a material configured to change between multiple phases, wherein the programmable portion is isolated from the first electrode by a first portion of the memory element, and wherein the programmable portion is isolated from the second electrode by a second portion of the memory element, each of the first and second portion having a material, the material of the first portion directly contacting the first electrode, the material of the second portion directly contactin the second electrode the memory element including an intermediate material between the first and second portions, the intermediate material being different from the material of each of the first portion, the second portion, and the programmable portion, and the intermediate material isolating the first portion from the second portion.

13. The method of claim 12 , wherein the memory element includes chalcogenide material.

14. The method of claim 12 , wherein the intermediate material includes one of TiN, ZrN, HfN, VN, NbN, TaN, TiC, ZrC, HfC, VC, NbC, TaC,TiB 2 , ZrB 2 , HfB 2 , VB 2 , NbB 2 , TaB 2 , Cr 3 C 2 , Mo 2 C, WC, CrB 2 , Mo 2 B5, W 2 B5, TiA1N, TiSiN, TiW, TaSiN, TiCN, SiC, B 4 C, WSix, MoSi 2 , NiCr, doped silicon, carbon, platinum, niobium, tungsten, and molybdenum.

15. The method of claim 12 , wherein the intermediate material has a resistance value lower than a resistance value of each of the first and second portions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2016
From: MICRON TECHNOLOGY, INC
To: OVONYX MEMORY TECHNOLOGY, LLC
Reel/Frame 039974/0496 →