IP Library Granted Patent US 9,209,273
Granted Patent B1
US 9,209,273 · App. 14/463,677 · Granted Dec 8, 2015

Method of fabricating metal gate structure

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Quick Facts
Patent No.
US 9,209,273
App. No.
14/463,677
Granted
Dec 8, 2015
Kind
B1
Abstract

A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

Claims (24)

1. A method for fabricating a metal gate structure, comprising:

providing a substrate, wherein a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed on the substrate, and the width of the first trench is less than the width of the second trench;

forming a mask layer to completely cover the second trench;

performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and

performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

2. The method according to claim 1 , wherein the width of the first trench is at least less than one-third of the width of the second trench.

3. The method according to claim 1 , further comprising forming a dielectric film to cover the first trench and the second trench before the step of performing the first etching process.

4. The method according to claim 3 , further comprising forming a metal compound at an interface between the dielectric film and the first metal layer before the step of performing the first etching process.

5. The method according to claim 4 , wherein the metal compound is a metal oxide or a metal nitride, and metal components of the metal compound is the same as at least one of metal components of the first metal layer.

6. The method according to claim 4 , wherein the metal compound is tungsten oxide, tungsten nitride or aluminum nitride.

7. The method according to claim 4 , wherein the metal compound is formed by applying an electrostatic field.

8. The method according to claim 4 , wherein the metal compound is completely removed during the first etching process.

9. The method according to claim 4 , further comprising forming another metal compound at an interface between the dielectric film and the second metal layer during the step of forming the metal compound.

10. The method according to claim 9 , wherein another metal compound is completely removed during the second etching process.

11. The method according to claim 1 , further comprising removing the mask layer before the second etching process.

12. The method according to claim 1 , wherein the height of the first metal layer is less than or equal to the height of the second metal layer when the second etching process is completed.

13. The method according to claim 1 , further comprising forming a dielectric cap layer to cover the first metal layer and the second metal layer after the second etching process, wherein the dielectric cap layer is in direct contact with the first metal layer and the second metal layer.

14. The method according to claim 13 , further comprising concurrently forming a metal compound at an interface between the dielectric cap layer and the first and second metal layers during the step of forming the dielectric cap layer.

15. The method according to claim 14 , wherein the metal compound is metal oxide or metal nitride.

16. The method according to claim 14 , wherein the metal compound is tungsten oxide, tungsten nitride or aluminum nitride.

17. The method according to claim 14 , wherein the metal compound is formed by applying an electrostatic field.

18. The method according to claim 13 , wherein the dielectric cap layer filling up the first trench and the second trench.

19. The method according to claim 1 , further comprising forming a first gate dielectric layer and a first gate material layer, wherein the first gate dielectric layer, the first gate material layer and the first metal layer are sequentially disposed in the first trench.

20. The method according to claim 1 , further comprising forming a first gate dielectric layer, a second gate dielectric layer, a first gate material layer and a second gate material layer, wherein the first gate dielectric layer, the first gate material layer and the first metal layer are sequentially disposed in the first trench, and the second gate dielectric layer, the second gate material layer and the second metal layer are sequentially disposed in the second trench.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2014
From: LIN, CHING-LING; HUANG, CHIH-SEN; TZOU, SHIH-FANG; LIN, CHIEN-TING; CHEN, YI-WEI; LIN, SHI-XIONG; CHEN, CHUN-LUNG; LIAO, KUN-YUAN; CHANG, FENG-YI; CHOU, HSIAO-PANG; LU, CHIA-LIN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 033568/0523 →