Ion-sensitive layer structure for an ion-sensitive sensor and method for manufacturing the same

1. A method for manufacturing an ion-sensitive structure for an ion-sensitive sensor, comprising the steps of:

providing a semiconductor substrate bearing an oxide layer; and

depositing and tempering a metal oxide layer and a metal layer, in order to obtain a layer sequence having a crystallized metal oxide layer and an oxidized and crystallized metal layer on the semiconductor substrate bearing the oxide layer, wherein:

the metal oxide layer and the metal layer have a same metal element; and

the coating thickness (dMOX) of the metal oxide layer is greater than the coating thickness (dMET) of the metal layer.

2. The method as claimed in claim 1 , wherein:

said step of depositing and tempering further comprises steps as follows:

depositing the metal oxide layer on the semiconductor substrate bearing the oxide layer, tempering at least the metal oxide layer, in order to obtain a crystallized metal oxide layer; depositing the metal layer on the crystallized metal oxide layer, and tempering the applied metal layer, in order to obtain an oxidized and crystallized metal layer.

3. The method as claimed in claim 1 , wherein:

said step of depositing and tempering further comprises steps as follows:

depositing the metal oxide layer on the semiconductor substrate bearing the oxide layer;

depositing the metal layer on the applied metal oxide layer; and

tempering the applied metal layer and the applied metal oxide layer, in order to obtain the crystallized metal oxide layer and the oxidized and crystallized metal layer on the semiconductor substrate bearing the oxide layer.

4. The method as claimed in claim 3 , wherein:

in said step of tempering, a first partial tempering is performed at an oxidation temperature, in order to oxidize the applied metal layer; and

a second partial tempering is performed at a crystallization temperature, in order to crystallize the applied metal oxide layer and the oxidized metal layer, in order to obtain the layer sequence with the crystallized metal oxide layer and the oxidized and crystallized metal layer.

5. The method as claimed in claim 1 , wherein:

the metal oxide layer is applied with a thickness of 25 to 400 nm, and the metal layer is applied with a thickness of 1 to 100 nm on the metal oxide layer.

6. The method as claimed in claim 5 , wherein:

the coating thickness for the applied metal oxide layer lies in a range of 50 to 200 nm; and

the coating thickness of the applied metal layer lies in a range between 3 and 30 nm.

7. The method as claimed in claim 1 , further comprising the step of:

applying and tempering an additional metal oxide layer and an additional metal layer on the first layer sequence, in order to obtain another layer sequence having an additional crystallized metal oxide layer and an additional oxidized and crystallized metal oxide layer on the first layer sequence, wherein:

the coating thickness dMOX 1 of the additional metal oxide layer is greater than the coating thickness of the additional metal layer dMET 1 ; and

the first layer sequence and the second layer sequence have a same metal element.

8. The method as claimed in claim 1 , further comprising the steps of:

repeating the step of applying and tempering a metal oxide layer and a metal layer a plurality of times, in order to obtain a plurality of double layer sequences having a crystallized metal oxide layer and an oxidized and crystallized metal layer applied thereon, wherein:

the coating thickness of the respective metal oxide layer is greater than the coating thickness of the respective metal layer; and

the applied layers have a same metal element.

9. The method as claimed in claim 8 , wherein:

said steps of depositing and tempering are performed, in order to apply two to four other double layer sequences of a crystallized metal oxide layer and an oxidized and crystallized metal layer.

10. The method as claimed in claim 8 , wherein:

a tempering is performed, in each case, after applying of a metal oxide layer or a metal layer, in order to obtain a crystallized metal oxide layer and/or an oxidized and crystallized metal layer.

11. The method as claimed in claim 8 , wherein:

one or more layer sequences having a metal oxide layer and a metal layer are applied alternately to one another; and

said step of tempering is performed on the applied layers, in order to obtain a plurality of crystallized metal oxide layers and a plurality of oxidized and crystallized metal layers.

12. The method as claimed in claim 1 , wherein:

said tempering is performed at a temperature of at least 600° C. as a crystallization procedure for producing the crystallized metal oxide layer and crystallized metal layer.

13. The method as claimed in claim 1 , wherein:

a pretempering at an oxidation temperature below 600° C. is performed before the tempering at the crystallization temperature, in order to perform an oxidation procedure at least for the applied metal layer before the crystallization procedure.

14. The method as claimed in claim 1 , wherein:

tantalum, hafnium, zirconium, titanium or aluminum is used as a metal element for the applied metal oxide layer or the applied metal oxide layers;

tantalum, hafnium, zirconium, titanium or aluminum is used as a metal element for the applied metal layer or the applied metal layers; and

the applied metal oxide layer or applied metal oxide layers and the applied metal layer or applied metal layers have a same metal element.

15. The method as claimed in claim 1 , wherein:

the metal oxide layer or metal oxide layers and the metal layer or metal layers is/are applied by sputtering, vapor deposition, a CVD process, a PVD process or an ALD process.

16. The method as claimed in claim 1 , wherein:

the oxide layer on the semiconductor substrate is obtained by means of a thermal oxidation procedure; and

the oxide layer provided on the semiconductor substrate has a coating thickness of 3 to 150 nm.

17. The method as claimed in claim 1 , wherein:

the semiconductor substrate comprises n- or p doped silicon material; and

the oxide layer comprises an amorphous silicon dioxide material.

18. The method as claimed in claim 1 , further comprising a step of:

applying a terminating layer before said step of tempering the applied metal layer and the applied metal oxide layer,

wherein the terminating layer is a metal oxide,

wherein the terminating layer is applied on the untempered metal layer, and

wherein the terminating layer and the

metal layer have a same metal element.

19. The method as claimed in claim 18 , further comprising a step of:

tempering the terminating layer, in order to obtain a crystallized, metal oxide, terminating layer.

20. The method as claimed in claim 19 , wherein:

said step of tempering the terminating layer is performed together with the tempering of the applied metal layer, said step of depositing and tempering further comprises steps as follows:

a) depositing the metal oxide layer on the semiconductor substrate bearing the oxide layer, tempering at least the metal oxide layer, in order to obtain a crystallized metal oxide layer; depositing the metal layer on the crystallized metal oxide layer, and tempering the applied metal layer, in order to obtain an oxidized and crystallized metal layer, or

b) together with the step of tempering the applied metal layer and the applied metal oxide layer, said step of depositing and tempering further comprises steps as follows: depositing the metal oxide layer on the semiconductor substrate bearing the oxide layer; depositing the metal layer on the applied metal oxide layer; and tempering the applied metal layer and the applied metal oxide layer, in order to obtain the crystallized metal oxide layer and the oxidized and crystallized metal layer on the semiconductor substrate bearing the oxide layer.

21. A method for manufacturing an ion-sensitive field effect transistor, comprising the steps of:

providing a semiconductor substrate having a source region and a drain region; and

producing a gate region having an ion-sensitive layer structure, wherein:

the ion-sensitive layer structure is produced according to a method as claimed in claim 1 .

22. A method for the read out of an ion-sensitive, capacitively readable, EIS sensor having an ion-sensitive layer structure, wherein the ion-sensitive layer structure is produced according to a method as claimed in claim 1 .

23. A method for manufacture of a light operated, ion-sensitive sensor having an ion-sensitive layer structure, wherein the ion-sensitive layer structure is produced according to a method as claimed in claim 1 .

24. An ion-sensitive sensor having an ion-sensitive structure, wherein the ion-sensitive structure is obtained by a method as claimed in claim 1 .

25. The ion-sensitive sensor as claimed in claim 24 and embodied as an ISFET element, capacitively readable EIS element or LAPS element.