IP Library › Granted Patent US 9,224,871
Granted Patent B2
US 9,224,871 · App. 14/466,314 · Granted Dec 29, 2015

Thin film transistor and method for manufacturing same

Inventors: Yuya Maeda (Kawasaki, JP); Hajime Yamaguchi (Kawasaki, JP); Tomomasa Ueda (Yokohama, JP); Kentaro Miura (Kawasaki, JP); Shintaro Nakano (Kawasaki, JP); Nobuyoshi Saito (Oota, JP); Tatsunori Sakano (Kawasaki, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L29/78696H01L29/0895H01L29/45H01L29/66969H01L29/78606H01L29/78693
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,224,871
App. No.
14/466,314
Granted
Dec 29, 2015
Kind
B2
Abstract

According to one embodiment, a thin film transistor includes a first insulating film, a gate electrode, a semiconductor layer, a gate insulator film, a second insulating film, a source electrode, a tunneling insulating portion, and a drain electrode. The semiconductor layer is provided between the gate electrode and the first insulating film, and includes an amorphous oxide. The gate insulator film is provided between the semiconductor layer and the gate electrode. The second insulating film is provided between the semiconductor layer and the first insulating film. The tunneling insulating portion is provided between the semiconductor layer and the source electrode, and between the semiconductor layer and the drain electrode, and between the first insulating film and the second insulating film. The tunneling insulating portion includes oxygen and at least one selected from aluminum and magnesium. A thickness of the tunneling insulating portion is 2 nanometers or less.

Claims (24)

1. A thin film transistor, comprising:

a gate electrode;

a first insulating film provided apart form the gate electrode in a first direction;

a semiconductor layer provided between the gate electrode and the first insulating film, the semiconductor layer including a first portion, a second portion, and a third portion, the second portion being apart from the first portion in a second direction intersecting the first direction, the third portion being provided between the first portion and the second portion, the semiconductor layer including an amorphous oxide;

a gate insulator film provided between the third portion and the gate electrode;

a second insulating film provided between the third portion and the first insulating film;

a source electrode;

a first tunneling insulating portion provided between the first portion and the source electrode, the first tunneling insulating portion including a first compound including oxygen and at least one selected from aluminum and magnesium, a thickness of the first tunneling insulating portion being 2 nanometers or less;

a drain electrode;

a second tunneling insulating portion provided between the second portion and the drain electrode, the second tunneling insulating portion including a second compound including oxygen and at least one selected from aluminum and magnesium, a thickness of the second tunneling insulating portion being 2 nanometers or less; and

a third tunneling insulating portion provided between the first insulating film and the second insulating film, the third tunneling insulating portion including a third compound including oxygen and at least one selected from aluminum and magnesium, a thickness of the third tunneling insulating portion being 2 nanometers or less.

2. The thin film transistor according to claim 1 , wherein a concentration of hydrogen included in the second insulating film is lower than a concentration of hydrogen included in the first insulating film.

3. The thin film transistor according to claim 1 , wherein a concentration of hydrogen included in the second insulating film is not less than 1×10 19 cm −3 and not more than 1×10 20 cm −3 .

4. The thin film transistor according to claim 1 , wherein a concentration of hydrogen included in the first insulating film is 1×10 21 cm −3 or more.

5. The thin film transistor according to claim 1 , wherein the second insulating film includes silicon oxide.

6. The thin film transistor according to claim 1 , wherein an arithmetic average roughness Ra of a surface of the first portion on the first tunneling insulating portion side is 0.5 nanometers or less.

7. The thin film transistor according to claim 1 , wherein the semiconductor layer includes oxygen and at least one selected from In, Ga, and Zn.

8. The thin film transistor according to claim 1 , wherein at least one selected from the first tunneling insulating portion, the second tunneling insulating portion, and the third tunneling insulating portion includes aluminum oxide.

9. The thin film transistor according to claim 1 , wherein at least one selected from the first tunneling insulating portion, the second tunneling insulating portion, and the third tunneling insulating portion includes magnesium oxide.

10. The thin film transistor according to claim 1 , wherein

the source electrode includes at least one selected from Ti, Al, Mo, Ta, and W, and

the drain electrode includes at least one selected from Ti, Al, Mo, Ta, and W.

11. The thin film transistor according to claim 1 , wherein the gate electrode includes at least one selected from Mo, Ta, and W.

12. The thin film transistor according to claim 1 , wherein the gate insulator film includes at least one selected from silicon oxide and silicon nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2014
From: MAEDA, YUYA; YAMAGUCHI, HAJIME; UEDA, TOMOMASA; MIURA, KENTARO; NAKANO, SHINTARO; SAITO, NOBUYOSHI; SAKANO, TATSUNORI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 033873/0841 →
Priority Claims (1)
JP 2013-196821 · Sep 24, 2013 · national
Continuity (1)
Related Publication 20150084042A1 · Mar 26, 2015