Semiconductor device and fabrication method thereof
View Patent ↗A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
1. A semiconductor device comprising:
a silicon substrate;
a gate insulating film over the silicon substrate;
a gate electrode formed over the gate insulating film;
a source region and a drain region formed in the silicon substrate;
a first SiGe mixed crystal region formed in the source region, a bottom of the first SiGe mixed crystal region being located shallower than a bottom of the source region;
a second SiGe mixed crystal region formed in the drain region, a bottom of the second SiGe mixed crystal region being located shallower than a bottom of the drain region;
a first silicide layer over the first SiGe mixed crystal region; and
a second silicide layer over the second SiGe mixed crystal region,
wherein a bottom of the first silicide layer and a bottom of the second silicide layer are located higher than a first boundary between the silicon substrate and the gate insulating film, and
wherein each of the first and second SiGe mixed crystal regions is defined by a plurality of facets that are (111) planes of the silicon substrate which form respective, mutually different angles with respect to a surface of the substrate under the gate insulating film.
2. The semiconductor device of claim 1 , wherein the first SiGe mixed crystal region comprises a first portion having a first Ge concentration,
the first silicide layer comprises a second portion having a second Ge concentration, and
the second Ge concentration is lower than the first Ge concentration.
3. The semiconductor device of claim 2 , wherein the first Ge concentration is greater than 20 atomic percent.
4. The semiconductor device of claim 2 , wherein the second Ge concentration is less than 20 atomic percent.
5. The semiconductor device of claim 2 , wherein the first Ge concentration is greater than 20 atomic percent and the second Ge concentration is less than 20 atomic percent.
6. The semiconductor device of claim 2 , wherein the second SiGe mixed crystal region comprises a third portion having a third Ge concentration,
the second silicide layer comprises a fourth portion having a fourth Ge concentration, and
the fourth Ge concentration is lower than the third Ge concentration.
7. The semiconductor device of claim 6 , wherein the first Ge concentration is greater than 20 atomic percent, and
the third Ge concentration is greater than 20 atomic percent.
8. The semiconductor device of claim 6 , wherein the second Ge concentration is less than 20 atomic percent, and
the fourth Ge concentration is less than 20 atomic percent.
9. The semiconductor device of claim 6 , wherein the first Ge concentration is greater than 20 atomic percent and the second Ge concentration is less than 20 atomic percent, and
the third Ge concentration is greater than 20 atomic percent and the fourth Ge concentration is less than 20 atomic percent.
10. The semiconductor device of claim 6 , further comprising a third silicide layer over the gate electrode,
wherein the third silicide layer is substantially free from Ge.
11. The semiconductor device of claim 2 , further comprising a third silicide layer over the gate electrode,
wherein the third silicide layer is substantially free from Ge.
12. The semiconductor device of claim 1 , wherein the first silicide layer and the second silicide layer are substantially free from Ge.
13. The semiconductor device of claim 12 , wherein the first SiGe mixed crystal region comprises a first portion that has a first Ge concentration,
the first silicide layer comprises a second portion that has a second Ge concentration, and
the second Ge concentration is lower than the first Ge concentration.
14. The semiconductor device of claim 13 , wherein the first Ge concentration is greater than 20 atomic percent.
15. The semiconductor device of claim 13 , wherein the second Ge concentration is less than 20 atomic percent.
16. The semiconductor device of claim 13 , wherein the first Ge concentration is greater than 20 atomic percent and the second Ge concentration is less than 20 atomic percent.
17. The semiconductor device of claim 13 , further comprising a third silicide layer over the gate electrode,
wherein the third silicide layer is substantially free from Ge.
18. The semiconductor device of claim 1 , further comprising a third silicide layer over the gate electrode.