IP Library Granted Patent US 9,362,389
Granted Patent B2
US 9,362,389 · App. 14/470,569 · Granted Jun 7, 2016

Polarization induced doped transistor

Inventors: Huili (Grace) Xing (Notre Dame, IN); Debdeep Jena (Notre Dame, IN); Kazuki Nomoto (Notre Dame, IN); Bo Song (Notre Dame, IN); Mingda Zhu (Notre Dame, IN); Zongyang Hu (Notre Dame, IN)
Assignee: University of Notre Dame du Lac
H01L29/7787H01L29/0619H01L29/1095H01L29/201H01L29/2003H01L29/205H01L29/8083
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Quick Facts
Patent No.
US 9,362,389
App. No.
14/470,569
Granted
Jun 7, 2016
Kind
B2
Abstract

A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.

Claims (40)

1. A III-V Nitride-based field effect transistor (FET) comprising:

a compositionally graded and polarization doped p-layer underlying at least one of a source, drain, gate, or body contact;

a compositionally graded and doped n-channel underlying at least one of the source or gate contact, wherein the n-channel is converted from the p-layer to the n-channel by ion implantation;

a drift region underlying the doped p-layer and the n-channel;

a n+region underlying the drift region; and

a drain underlying the n+region.

2. A field effect transistor as defined in claim 1 , wherein the n-channel is converted via ion implantation of silicon.

3. A field effect transistor as defined in claim 1 wherein the drift region is a doped n-layer.

4. A field effect transistor as defined in claim 3 , wherein the drift region is a doped n-layer comprising GaN.

5. A field effect transistor as defined in claim 1 , wherein the p-layer comprises AlGaN.

6. A field effect transistor as defined in claim 1 , wherein the transistor forms a vertical junction field effect transistor.

7. A field effect transistor as defined in claim 1 further comprising a substrate between the buffer and the drain.

8. A field effect transistor as defined in claim 7 , wherein the substrate is GaN.

9. A metal-oxide semiconductor field effect transistor (MOSFET) comprising:

a compositionally graded AlGaN epitaxial structure;

an n-channel formed in the upper portion of the epitaxial structure via ion implantation;

a pair of n+regions formed in the upper portion of the epitaxial structure laterally displaced on either side of the n-channel, wherein the n+regions are formed via at least one of ion implantation or regrowth;

a p doped region formed in the upper portion of the epitaxial structure laterally displaced on either side of the n+regions and in ohmic contact with a p layer;

an AlGaN top barrier, a gate contact overlaying the n-channel;

a source overlaying at least a portion of the upper portion of the epitaxial structure; and

a drain underlying at least a portion of a lower portion of the epitaxial structure.

10. A metal-oxide semiconductor field effect transistor as defined in claim 9 , wherein the n-channel is formed via ion implantation of silicon.

11. A metal-oxide semiconductor field effect transistor as defined in claim 9 , wherein the n-channel comprises AlGaN.

12. A metal-oxide semiconductor field effect transistor as defined in claim 9 , wherein the lower portion of the epitaxial structure comprises GaN.

13. A metal-oxide semiconductor field effect transistor as defined in claim 9 , further comprising edge terminations on each side of the epitaxial structure.

14. A metal-oxide semiconductor field effect transistor as defined in claim 12 , wherein the edge termination is formed via isolation ion implantation.

15. A metal-oxide semiconductor heterostructure field effect transistor comprising:

an AlGaN compositionally graded pGaN layer;

a GaN channel overlaying the pGaN layer;

at least two n-doped regions formed in the upper portion of the GaN channel laterally displaced from one another;

at least one p-doped region formed in the upper portion of the GaN channel in ohmic contact with the graded pGaN layer;

a gate dielectric and a gate contact overlaying the GaN channel;

a source overlaying at least a portion of one of the n-doped regions; and

a drain overlaying at least a portion of the other of the n-doped region.

16. A field effect transistor as defined in claim 1 , wherein the compositionally graded and doped n-channel is graded in the different direction from the p-layer.

17. A field effect transistor as defined in claim 1 , wherein the compositionally graded and doped n-channel is adjacent to the p-layer.

18. A field effect transistor as defined in claim 17 , where the compositional grading is equal at the juncture between the n and p layer.

19. A field effect transistor as defined in claim 1 , wherein the graded and doped n-channel comprises compositionally graded AlGaN.

20. A field effect transistor as defined in claim 4 , wherein the drift region is a doped n-layer further comprising linearly graded n-type AlGaN.

21. A metal-oxide semiconductor field effect transistor as defined in claim 12 , wherein the lower portion of the epitaxial structure further comprises linearly composition graded doped n-type AlGaN.

Assignments (2)
CONFIRMATORY LICENSE Recorded Sep 16, 2015
From: UNIVERSITY OF NOTRE DAME
To: U.S. DEPARTMENT OF ENERGY
Reel/Frame 036579/0118 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: XING, HUILI (GRACE); JENA, DEBDEEP; NOMOTO, KAZUKI; SONG, BO; ZHU, MINGDA; HU, ZONGYANG
To: UNIVERSITY OF NOTRE DAME DU LAC
Reel/Frame 034138/0197 →
Continuity (2)
Provisional Application 61870495 · Aug 27, 2013
Related Publication 20150060876A1 · Mar 5, 2015