Methods for mitigating system interrupts for an electronic device

1. A method for operating an electronic device that includes a main processor and a coprocessor for interfacing with an input-output device, comprising:

with the main processor, passing a group of submitted transactions into a submission queue;

in response to receiving the group of submitted transactions in the submission queue, using the main processor to assert a submission interrupt signal to indicate to the coprocessor that the group of submitted transactions is pending in the submission queue;

in response to receiving the asserted submission interrupt signal, using the coprocessor to obtain the group of submitted transactions from the submission queue;

while the coprocessor is processing the group of submitted transactions obtained from the submission queue, temporarily disabling use of the submission interrupt signal to avoid interrupts to the coprocessor;

with the coprocessor, passing a group of completed transactions into a completion queue; and

in response to receiving the group of completed transactions in the completion queue, using the coprocessor to assert a completion interrupt signal to indicate to the main processor that the group of completed transactions is pending in the completion queue, wherein the completion interrupt signal is different than the submission interrupt signal;

in response to receiving the asserted completion interrupt signal, using the main processor to obtain the group of completed transactions from the completion queue; and

while the main processor is processing the group of completed transactions obtained from the completion queue, temporarily disabling use of the completion interrupt signal to avoid interrupts to the main processor.

2. The method defined in claim 1 , further comprising:

monitoring a fill level of the submission queue using a coprocessor communications management module at the main processor, wherein the coprocessor communications management module is also used to assert the submission interrupt signal.

3. The method defined in claim 2 , further comprising:

monitoring a fill level of the completion queue using a main processor communications management module at the coprocessor, wherein the main processor communications module is also used to assert the completion interrupt signal.

4. The method defined in claim 1 , wherein passing the group of submitted transactions into the submission queue comprises forwarding a complete burst of continuous transactions to the submission queue.

5. The method defined in claim 3 , further comprising:

with the main processor communications management module, sending an alert to the main processor when the fill level of the submission queue falls below a predetermined threshold.

6. The method defined in claim 2 , further comprising:

with the coprocessor communications management module, sending an alert to the coprocessor when the fill level of the completion queue falls below a predetermined threshold.

7. The method defined in claim 1 , wherein the electronic device also includes a system memory that is accessible to both the main processor and the coprocessor, the method further comprising:

storing contents of the submission queue and the completion queue in the system memory.

8. An electronic device, comprising:

an applications processor for running user applications on the electronic device;

an input-output device; and

an input-output subsystem that is coupled between the applications processor and the input-output device, wherein the input-output subsystem includes a coprocessor for actively managing communications with the input-output device, wherein the input-output subsystem receives a subsystem clock, and wherein the subsystem clock is ungated only when the input-output subsystem is actively processing transactions generated by the applications processor.

9. The electronic device defined in claim 8 , wherein the input-output subsystem further includes an input-output host controller, wherein an input-output bus is interposed between the input-output host controller and the input-output device, and wherein the input-output bus is controlled by a bus clock signal that is ungated only when the input-output subsystem is actively communicating with the input-output host controller.

10. The electronic device defined in claim 9 , wherein the applications processor is configured to output a submission interrupt doorbell to the input-output subsystem, wherein the input-output host controller is controlled by a host controller clock signal, and wherein the host controller clock signal is ungated after the input-output subsystem receives the submission interrupt doorbell and is gated before the input-output subsystem outputs a completion interrupt doorbell to the applications processor.

11. The electronic device defined in claim 8 , wherein the coprocessor comprises a transactions management module configured to receive a submission interrupt signal from the applications processor.

12. The electronic device defined in claim 11 , wherein the coprocessor further comprises a driver module configured to receive a command from the transactions management module, and wherein the command directs the driver module to initiate communications with a peripheral input-output device coupled to the input-output subsystem.

13. The electronic device defined in claim 12 , wherein the driver module is further configured to receive an additional interrupt signal from the peripheral input-output device.

14. A method of operating an electronic device comprising:

with an applications processor, generating transactions;

with an input-output subsystem, receiving a subsystem clock, wherein the input-output subsystem is coupled between the applications processor and an input-output device and wherein the input-output subsystem includes a coprocessor;

with the coprocessor, actively managing communications with the input-output device; and

ungating the subsystem clock only when the input-output subsystem is actively processing the transactions.

15. The method of claim 14 , wherein the input-output subsystem further comprises an input-output host controller, the method further comprising:

controlling an input-output bus between the input-output host controller and the input-output device using a bus clock signal; and

ungating the bus clock signal while the input-output subsystem is actively communicating with the input-output host controller.

16. The method of claim 15 , further comprising:

with the applications processor, outputting a submission interrupt doorbell; and

with the input-output subsystem, receiving the submission interrupt doorbell.

17. The method of claim 16 , further comprising:

using a host controller clock signal to control the input-output host controller; and

in response to the input-output subsystem receiving the submission interrupt doorbell, ungating the host controller clock signal.

18. The method of claim 17 , further comprising:

with the input-output subsystem, outputting a completion interrupt doorbell to the applications processor.

19. The method of claim 18 , further comprising:

prior to outputting the completion interrupt doorbell, gating the host controller clock signal.

20. The method of claim 18 , further comprising:

in response to receiving the submission interrupt doorbell, using the coprocessor to obtain at least some of the transactions from a submission queue; and

in response to receiving the completion interrupt doorbell, using the applications processor to obtain completed transactions from a completion queue.