Single node power management for multiple memory devices
View Patent ↗Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.
1. An apparatus comprising:
a node to couple to a plurality of memory devices;
memory cells; and
a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the plurality of memory devices, and to perform the particular stage of the operation after the request is acknowledged;
another memory device, and the node, the memory cells, and the module are parts of the other memory device, wherein the other memory device includes a clock generator to generate a clock signal, and the module is configured to use timing of the clock signal during a process to acknowledge the request, wherein the module is configured to stop oscillating the clock signal when the particular stage of the operation is performed.
2. The apparatus of claim 1 , wherein the module includes an arbiter responsive to the at least one change in the level of the signal to acknowledge the request.
3. The apparatus of claim 1 , wherein the arbiter includes a first-in-first-out structure.
4. An apparatus comprising:
a node; and
a plurality of dice coupled to the node, each die of the plurality of dice configured to monitor a signal at the node and determine an identity of a particular die among the dice in response to a change in a level of the signal, the change in the level of the signal indicating a request made by the particular die to perform a stage of an operation on memory cells of the particular die, wherein each die of the plurality of dice is configured to perform a process to acknowledge the request and allow the stage of the operation to be performed after the request is acknowledged, wherein each die of the plurality of dice includes a clock generator to generate a clock signal, wherein the clock generator in each die of the plurality of dice is configured to start oscillating the clock signal in response to the change in the level of the signal and to stop oscillating the clock signal when the stage of the operation is performed.
5. The apparatus of claim 4 , wherein each die of the plurality of dice includes an arbiter configured store information associated with the request and to allow the stage of the operation to be performed based on an order indicated by the information.
6. The apparatus of claim 4 , wherein the particular die is configured to charge at least one data line associated with the memory cells when the stage of the operation is performed.
7. The apparatus of claim 4 , wherein the node is part of a conductive path coupling to the dice, and the conductive path includes a conductive wire.
8. A method comprising:
starting an operation on memory cells;
making a request to perform a particular stage of the operation, wherein making the request includes causing a first change in a level of a signal at a node during a first time interval;
causing a second change in a level of the signal on the node during a second time interval in a process of acknowledging the request; and
performing the stage of the operation after the request is acknowledged.
9. The method of claim 8 , wherein the operation includes one of a read operation, a write operation, and an erase operation.
10. The method of claim 8 , wherein the stage of the operation consumes a higher amount of current than another stage of the operation.
11. The method of claim 8 , further comprising:
generating a clock signal in response to the first change in the level of the signal, wherein causing the second change in the level of the signal is based on timing of the clock signal.
12. The method of claim 8 , further comprising:
changing content of an arbiter when the request is acknowledged, wherein performing the stage of the operation follows an order based on the content of the arbiter.
13. The method of claim 8 , wherein causing each of the first and second changes in the level of the signal at the node includes causing the level of the signal to change from a higher level to a lower level.
14. A method comprising:
monitoring a signal on a node coupled to a plurality of memory devices, wherein monitoring is performed by each memory device of the plurality of memory devices;
determining an identity of a particular memory device among the memory devices in response to a change in a level of the signal, wherein the change in the level of the signal indicates a request made by the particular memory device to perform a stage of an operation on memory cells of the particular memory device, and determining the identity of the particular memory device is performed by each memory device of the plurality of memory devices;
acknowledging the request made by the particular memory device after the identity of the particular memory device is determined; and
performing the stage of the operation after acknowledging the request, wherein determining the identity of the particular memory device includes:
generating a plurality of rising edges in the signal after the change in the level of the signal occurs;
generating counts having a different count value between two different consecutive edges of the signal, wherein each of the counts has a count value matching a unique memory device identification of a memory device among the memory devices; and
causing an additional change in the level of the signal between two consecutive edges when the count value matches the identity of the particular memory device.
15. The method of claim 14 , wherein determining the identity of the particular memory device further includes sampling a portion of the signal between each two consecutive edges of the signal at the node, and sampling is performed by each memory device of the plurality of memory devices.
16. The method of claim 15 , wherein determining the identity of the particular memory device includes:
generating clock signals in the memory devices, such that each of the clock signals is generated by one of the memory devices, wherein timing for causing the additional change in the level of the signal and for sampling the signal is based on timing of respective clock signals in the memory devices.
17. A method comprising:
monitoring a signal on a node coupled to a plurality of memory devices, wherein monitoring is performed by each memory device of the plurality of memory devices;
determining an identity of a particular memory device among the memory devices in response to a change in a level of the signal, wherein the change in the level of the signal indicates a request made by the particular memory device to perform a stage of an operation on memory cells of the particular memory device, and determining the identity of the particular memory device is performed by each memory device of the plurality of memory devices;
acknowledging the request made by the particular memory device after the identity of the particular memory device is determined; and
performing the stage of the operation after acknowledging the request, wherein acknowledging the request includes changing content of an arbiter in each memory device of the plurality of memory devices based on the identity of the particular memory device, wherein performing the stage of the operation is performed by the particular memory device based on an order indicated by the content of the arbiter.