Thin film transistor and display panel including the same
Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.
1. A thin film transistor, comprising:
a gate electrode on a substrate, wherein the gate electrode includes a gate area with respect to the substrate;
a channel layer overlapping the gate electrode, wherein the channel layer includes a channel area with respect to the substrate;
a gate dielectric layer disposed between the gate electrode and the channel layer;
a source electrode and a drain electrode electrically connected to two parts of the channel layer; and
a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the passivation layer has a planar surface;
a via hole through the passivation layer to expose a part of the drain electrode; and
a conductive pattern on the planar surface of the passivation layer to serve as a pixel electrode, wherein the conductive pattern contacts the drain electrode through the via hole,
wherein the channel layer comprises an oxide semiconductor, and
wherein the channel area falls within the gate area.
2. The thin film transistor as claimed in claim 1 , further comprising an insulating capping layer covering the channel layer.
3. The thin film transistor as claimed in claim 2 , wherein a bottom surface of the insulating capping layer and a top surface of the channel layer have a substantially similar width.
4. The thin film transistor as claimed in claim 3 , wherein the bottom surface of the insulating capping layer and the top surface of the channel layer have a width difference of 0 μm to 2 μm.
5. The thin film transistor as claimed in claim 1 , wherein the source electrode and the drain electrode overlie two edge parts of the gate electrode.
6. The thin film transistor as claimed in claim 1 , wherein the material of the gate dielectric layer is selected from a group consisting of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or combinations thereof.
7. The thin film transistor as claimed in claim 1 , wherein the material of the oxide semiconductor is selected from a group consisting of zinc oxide, indium oxide, indium gallium zinc oxide, tin oxide, or combinations thereof.
8. A display panel, comprising:
a substrate;
a thin film transistor on the substrate, comprising:
a gate electrode, wherein the gate electrode includes a gate area respect to the substrate;
a channel layer overlapping the gate electrode, wherein the channel layer includes a channel area respect to the substrate;
a gate dielectric layer disposed between the gate electrode and the channel layer;
a source electrode and a drain electrode electrically connecting two parts of the channel layer;
a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the passivation layer has a planar surface;
a via hole through the passivation layer to expose a part of the drain electrode; and
a conductive pattern on the planar surface of the passivation layer to serve as a pixel electrode, wherein the conductive pattern contacts the drain electrode through the via hole,
wherein the channel layer comprises an oxide semiconductor,
wherein the channel area falls in the gate area.
9. The display panel as claimed in claim 8 further includes an insulating capping layer covering the channel layer.
10. The display panel as claimed in claim 9 , wherein a bottom surface of the insulating capping layer and a top surface of the channel layer have a substantially similar width.
11. The display panel as claimed in claim 10 , wherein the bottom surface of the insulating capping layer and the top surface of the channel layer have a width difference of 0 μm to 2 μm.
12. The display panel as claimed in claim 8 , wherein the source electrode and the drain electrode overlie two edge parts of the gate electrode.
13. The display panel as claimed in claim 8 , wherein the material of the gate dielectric layer is selected from a group consisting of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or combinations thereof.
14. The display panel as claimed in claim 8 , wherein the material of the oxide semiconductor is selected from a group consisting of zinc oxide, indium oxide, indium gallium zinc oxide, tin oxide, or combinations thereof.