IP Library Granted Patent US 9,287,288
Granted Patent B2
US 9,287,288 · App. 14/479,474 · Granted Mar 15, 2016

Semiconductor memory device

Inventors: Naoki Yasuda (Mie, JP); Yoshiaki Fukuzumi (Yokkaichi, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/11582H01L27/11565
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Quick Facts
Patent No.
US 9,287,288
App. No.
14/479,474
Granted
Mar 15, 2016
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers each provided between adjacent ones of the electrode layers; and a columnar portion penetrating through the stacked body and extending in a stacking direction of the stacked body. The columnar portion includes a channel body extending in the stacking direction; a charge storage film provided between the channel body and the electrode layer; and a gap provided between the charge storage film and the electrode layer.

Claims (47)

1. A semiconductor memory device comprising:

a substrate;

a stacked body provided above the substrate, the stacked body being including a plurality of electrode layers and a plurality of insulating layers each provided between adjacent ones of the electrode layers; and

a columnar portion penetrating through the stacked body and extending in a stacking direction of the stacked body,

the columnar portion including:

a channel body extending in the stacking direction;

a charge storage film provided between the channel body and the electrode layer; and

a gap provided between the charge storage film and the electrode layer and

a first insulating film provided between the charge storage film and the electrode layer; the insulating film overlapping a part of the electrode layer and a part of the gap when viewed along a first direction parallel to a surface of the substrate.

2. The semiconductor memory device according to claim 1 , wherein the first insulating film is provided between the gap and the electrode layer.

3. The semiconductor memory device according to claim 2 , wherein the first insulating film contains silicon and oxygen.

4. The semiconductor memory device according to claim 1 , wherein the first insulating film is provided between the charge storage film and the gap.

5. The semiconductor memory device according to claim 2 , further comprising:

a second insulating film provided between the charge storage film and the gap, the second insulating film overlapping at least a part of the electrode layer when viewed along the first direction.

6. The semiconductor memory device according to claim 5 , wherein the second insulating film comprises at least one of silicon oxide or silicon oxynitride.

7. The semiconductor memory device according to claim 1 , further comprising a second gap provided between the charge storage film and the channel body.

8. The semiconductor memory device according to claim 2 , wherein the first insulating film is provided directly on the electrode layer, the first insulating film having a higher dielectric constant than silicon oxide.

9. The semiconductor memory device according to claim 1 , wherein the charge storage film is provided in a cylindrical shape surrounding the channel body, the charge storage film extends in the stacking direction, the gap is provided in a cylindrical shape surrounding the charge storage film and the gap is extending in the stacking direction.

10. The semiconductor memory device according to claim 1 , further comprising an interlayer insulating layer provided on the stacked body,

a part of the interlayer insulating layer being filled between the charge storage film provided in an upper end portion of the columnar portion and the stacked body, and being located on the gap.

11. The semiconductor memory device according to claim 1 , further comprising a tunnel insulating film provided between the charge storage film and the channel body.

12. A semiconductor memory device comprising:

a stacked body including a plurality of electrode layers alternately stacked with a plurality of insulating layers, the stacked body including a first electrode layer, a first insulating layer, a second electrode layer and a second insulating layer, the second electrode layer being provided on the first insulating layer, the first insulating layer being provided on the first electrode layer, and the first electrode layer being provided on the second insulating layer;

a columnar portion penetrating through the stacked body and extending in a stacking direction of the stacked body,

the columnar portion including:

a channel body extending in the stacking direction;

a charge storage film provided between the channel body and the electrode layer;

a gap extending in the stacking direction, the gap being provided between the charge storage film and the electrode layer, the gap being provided along the first insulating layer, first electrode layer, second insulating layer and second electrode layer.

13. The semiconductor memory device according to claim 12 , wherein the stacked body further includes a third insulating layer provided on the second electrode layer, the gap being provided along the third insulating layer.

14. The semiconductor memory device according to claim 12 , wherein the gap is provided continuously along the plurality of electrode layers and the plurality of insulating layers.

15. The semiconductor memory device according to claim 12 , further comprising:

an additional columnar portion penetrating through the stacked body and extending in the stacking direction,

the additional columnar portion including:

an additional channel body extending in the stacking direction;

an additional charge storage film provided between the additional channel body and the electrode layer; and

an additional gap extending in the stacking direction, the additional gap being provided between the additional charge storage film and the additional electrode layer, the additional gap being provided along the first insulating layer, first electrode layer and the second insulating layer.

16. The semiconductor memory device according to claim 12 , further comprising:

a block insulating film provided between the gap and the electrode layer, and containing silicon and oxygen.

17. The semiconductor memory device according to claim 12 , further comprising:

a block insulating film provided between the charge storage film and the gap, and containing silicon and oxygen.

18. The semiconductor memory device according to claim 12 , further comprising:

a first block insulating film provided between the gap and the electrode layer, and containing silicon and oxygen,

a second block insulating film provided between the charge storage film and the gap, and containing silicon and oxygen.

19. The semiconductor memory device according to claim 12 , further comprising:

a second gap provided between the charge storage film and the channel body.

20. The semiconductor memory device according to claim 12 , further comprising:

a cap film provided directly on the electrode layer, the cap film being provided between the gap and the electrode layer, the first cap film having a higher dielectric constant than silicon oxide.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2014
From: YASUDA, NAOKI; FUKUZUMI, YOSHIAKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 034099/0771 →
Priority Claims (1)
JP 2014-021130 · Feb 6, 2014 · national
Continuity (1)
Related Publication 20150221665A1 · Aug 6, 2015