Semiconductor package structure and method for manufacturing the same
View Patent ↗A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n≧1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.
1. A semiconductor package structure, comprising:
a substrate having a first side, a second side and an opening extending from the first side to the second side, wherein the substrate comprises a redistribution layer and a via; and
a die stack of n die(s) disposed in the opening, wherein n≧1;
wherein the thickness of the substrate is substantially the same as the thickness of the die stack, and the redistribution layer and the via do not overlap with the die stack in a top view.
2. The semiconductor package structure according to claim 1 , wherein the substrate is a wafer or a panel.
3. The semiconductor package structure according to claim 1 , wherein one of the n dies is different from another one of the n dies.
4. The semiconductor package structure according to claim 1 , further comprising:
a first adhesive insulating layer disposed on the first side of the substrate and between the substrate and the die stack; and
a second adhesive insulating layer disposed on the second side of the substrate.
5. The semiconductor package structure according to claim 4 , wherein the first adhesive insulating layer and the second adhesive insulating layer comprise a light-sensitive adhesive.
6. The semiconductor package structure according to claim 4 , further comprising:
at least one first circuit layer disposed on the first side of the substrate, the at least one first circuit layer comprising pads; and
at least one second circuit layer disposed on the second side of the substrate, the at least one second circuit layer comprising pads.
7. The semiconductor package structure according to claim 6 , further comprising:
a first passivation layer disposed on the at least one first circuit layer, the first passivation layer exposing the pads of the at least one first circuit layer; and
a second passivation layer disposed on the at least one second circuit layer, the second passivation layer exposing the pads of the at least one second circuit layer.
8. The semiconductor package structure according to claim 7 , further comprising:
a die disposed on the first passivation layer and electrically connected to the pads of the at least one first circuit layer.