IP Library Granted Patent US 9,430,417
Granted Patent B2
US 9,430,417 · App. 14/479,703 · Granted Aug 30, 2016

Sequential memory access operations

Inventor: Toru Tanzawa (Tokyo, JP)
Assignee: Micron Technology, Inc.
G06F13/1657G06F12/0623G06F13/1694G06F2212/2532
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Quick Facts
Patent No.
US 9,430,417
App. No.
14/479,703
Granted
Aug 30, 2016
Kind
B2
Abstract

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

Claims (59)

1. A method of operating a memory, comprising:

performing a memory access operation;

obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation;

stopping the memory access operation;

determining whether to pull down a voltage level of a particular access line used for the memory access operation prior to sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation;

when it is determined to pull down the voltage level of the particular access line, pulling down the voltage level of the particular access line prior to sharing charge between the access lines used for the memory access operation and the access lines to be used for the subsequent memory access operation;

sharing charge between the access lines used for the memory access operation and the access lines to be used for the subsequent memory access operation; and

performing the subsequent memory access operation.

2. The method of claim 1 , wherein obtaining an address corresponding to a subsequent memory access operation comprises receiving the address from an external controller.

3. The method of claim 1 , wherein obtaining an address corresponding to a subsequent memory access operation comprises determining the address corresponding to the subsequent memory access operation from an address corresponding to the memory access operation.

4. The method of claim 3 , wherein determining the address corresponding to the subsequent memory access operation from an address corresponding to the memory access operation comprises toggling one or more bits of the address corresponding to the memory access operation.

5. The method of claim 1 , wherein the memory access operation and the subsequent memory access operation are each of a type selected from the group consisting of a program operation, a read operation and an erase operation.

6. The method of claim 5 , wherein the memory access operation and the subsequent memory access operation are different types of memory access operations.

7. The method of claim 1 , wherein the memory access operation and the subsequent memory access operation are performed in response to a single command.

8. The method of claim 1 , wherein stopping the memory access operation comprises completing the memory access operation or suspending the memory access operation.

9. The method of claim 1 , further comprising:

obtaining an address corresponding to a next subsequent memory access operation prior to stopping the subsequent memory access operation;

stopping the subsequent memory access operation;

sharing charge between access lines used for the subsequent memory access operation and access lines to be used for the next subsequent memory access operation; and

performing the next subsequent memory access operation.

10. The method of claim 9 , wherein stopping the memory access operation comprises suspending the memory access operation and wherein performing the next subsequent memory access operation comprises resuming the memory access operation.

11. The method of claim 9 , further comprising discharging the access lines used for the memory access operation after sharing charge with the access lines to be used for the subsequent memory access operation.

12. The method of claim 9 , wherein the access lines used for the memory access operation are not discharged after sharing charge with the access lines to be used for the subsequent memory access operation.

13. The method of claim 1 , wherein pulling down the voltage level of the particular access line comprises pulling the voltage level of the particular access line down to a voltage level of the remaining access lines used for the memory access operation.

14. A method of operating a memory, comprising:

performing a memory access operation;

obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation;

stopping the memory access operation;

determining whether sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation is desired;

if sharing charge is desired, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation; and

performing the subsequent memory access operation.

15. The method of claim 14 , wherein determining whether sharing charge is desired comprises determining whether sharing charge would result in at least one of reduction in power draw for the subsequent memory access operation or a reduction in access time of the subsequent memory access operation.

16. The method of claim 14 , further comprising discharging the access lines used for the memory access operation after sharing charge.

17. The method of claim 14 , wherein stopping the memory access operation comprises suspending the memory access operation, the method further comprising:

maintaining the shared charge on the access lines used for the memory access operation after disconnecting the access lines used for the memory access operation from the corresponding access lines to be used for the subsequent memory access operation.

18. A method of operating a memory, comprising:

performing a memory access operation;

obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation;

stopping the memory access operation;

determining whether sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation is desired;

when sharing charge is desired:

connecting the access lines used for the memory access operation with corresponding access lines to be used for the subsequent memory access operation;

sharing charge between the connected corresponding access lines; and

disconnecting the access lines used for the memory access operation from the corresponding access lines to be used for the subsequent memory access operation; and

performing the subsequent memory access operation.

19. A method of operating a memory, comprising:

performing a memory access operation;

obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation;

stopping the memory access operation;

determining whether sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation is desired;

when sharing charge is desired:

connecting the access lines used for the memory access operation with corresponding access lines to be used for the subsequent memory access operation;

sharing charge between the connected corresponding access lines; and

disconnecting the access lines used for the memory access operation from the corresponding access lines to be used for the subsequent memory access operation; and

performing the subsequent memory access operation;

wherein connecting the access lines used for the memory access operation with corresponding access lines to be used for the subsequent memory access operation comprises, for each access line used for the memory access operation, concurrently connecting that access line and its corresponding access line to be used for the subsequent memory access operation to a global access line common to those corresponding access lines.

20. The method of claim 19 , further comprising isolating one or more of the global access lines from a corresponding driver for each of the one or more global access lines.

21. The method of claim 19 , further comprising floating each global access line.

22. The method of claim 19 , wherein sharing charge between the connected corresponding access lines comprises, for each access line used for the memory access operation, sharing charge for that access line through its global access line to the corresponding access line to be used for the subsequent memory access operation.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2015
From: TANZAWA, TORU
To: MICRON TECHNOLOGY, INC
Reel/Frame 035267/0161 →
Continuity (1)
Related Publication 20160070663A1 · Mar 10, 2016