Semiconductor Die Having Fine Pitch Electrical Interconnects
A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF 4 plasma treatment.
1 - 32 . (canceled)
33 . A method for making a die assembly, comprising:
providing a die having interconnect features on a surface thereof;
forming an electrically insulative coating on the die;
forming an opening exposing a selected one of the interconnect features;
applying a curable interconnect material in contact with the exposed interconnect feature;
curing the interconnect material.
34 . The method of claim 33 wherein forming the coating comprises forming a coating by vapor deposition.
35 . The method of claim 33 wherein forming the coating comprises forming a coating by liquid phase deposition.
36 . The method of claim 33 wherein forming the coating comprises forming a coating by solid phase deposition.
37 . The method of claim 34 wherein forming an opening comprises carrying out a laser ablation procedure.
38 . The method of claim 33 wherein the interconnect material includes a curable electrically conductive polymer and applying the interconnect material comprises applying the interconnect material in a flowable form.
39 . The method of claim 33 wherein the interconnect material includes an electrically conductive ink and applying the interconnect material comprises applying the interconnect material in a flowable form.
40 . The method of claim 33 wherein the exposed interconnect feature comprises an interconnect pad on the die.
41 . The method of claim 33 , further comprising mounting the die on a support.
42 . The method of claim 41 , wherein the exposed interconnect feature comprises a bond site on the support.
43 . The method of claim 33 , further comprising treating the coated die with a CF4 plasma.
44 . The method of claim 43 wherein treating the coated die with a CF4 plasma is carried out prior to forming the opening.
45 . The method of claim 43 wherein treating the coated die with a CF4 plasma is carried out subsequent to forming the opening.
46 . The method of claim 33 , further comprising performing a plasma clean subsequent to forming openings.
47 . A manufacturing method comprising:
obtaining an integrated circuit comprising a surface comprising a dielectric region;
treating the surface with halogen containing plasma; then
applying a curable interconnect material onto the dielectric region; and
curing the interconnect material;
wherein treating the surface with halogen containing plasma reduces wettability of the dielectric region to the curable interconnect material.
48 . The method of claim 49 wherein the dielectric region comprises a polymer.
49 . The method of claim 48 wherein the interconnect material comprises a polymer.
50 . The method of claim 49 wherein the halogen containing plasma comprises a compound of fluorine and carbon.
51 . The method of claim 49 wherein the compound of fluorine and carbon is CF4.
52 . The method of claim 47 wherein the integrated circuit comprises an interconnect feature, and said applying the curable interconnect material comprises applying the curable interconnect material onto the interconnect feature.