Semiconductor light emitting device
View Patent ↗According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a p-side metal pillar, an n-side metal pillar, and an insulator. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side metal pillar includes a p-side external terminal. The n-side metal pillar includes an n-side external terminal. At least one selected from an area and a planar configuration of the p-side external terminal is different from at least one selected from an area and a planar configuration of the n-side external terminal.
1. A semiconductor light emitting device, comprising:
a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer provided between the first surface and the second surface;
a p-side electrode provided on the semiconductor layer;
an n-side electrode provided on the semiconductor layer;
a p-side metal pillar provided on the second surface side, and electrically connected to the p-side electrode;
an n-side metal pillar provided apart from the p-side metal pillar on the second surface side, and electrically connected to the n-side electrode; and
an insulator provided at least between the p-side metal pillar and the n-side metal pillar, the p-side metal pillar including a p-side external terminal exposed from the insulator at a surface different from a surface connected to the p-side electrode,
the n-side metal pillar including an n-side external terminal exposed from the insulator at a surface different from a surface connected to the n-side electrode,
a center line dividing a surface at which the p-side external terminal and the n-side external terminal are exposed from the insulator into two equal parts, the p-side external terminal and the n-side external terminal separated by the center line,
a planar configuration of the p-side external terminal being different from a planar configuration of the n-side external terminal, and
an area of the p-side external terminal being greater than an area of the n-side external terminal.
2. The device of claim 1 , wherein the n-side external terminal is exposed from the insulator at a surface which faces a same direction as the surface where the p-side external terminal is exposed.
3. The device of claim 1 , wherein the p-side external terminal is formed in a first configuration, the n-side external terminal is formed in a second configuration, the second configuration being the first configuration without a portion.
4. The device of claim 1 , wherein the insulator covers all side surfaces of the p-side metal pillar and the n-side metal pillar.
5. The device of claim 1 , further comprising:
an insulating layer provided on the second surface side, the insulating layer having a first via communicating with the p-side electrode and a second via communicating with the n-side electrode;
a p-side interconnect layer provided at least inside the first via, and electrically connected to the p-side electrode; and
an n-side interconnect layer provided apart from the p-side interconnect layer inside the second via and on an interconnect surface of the insulating layer, the interconnect surface opposite to the semiconductor layer, the n-side interconnect layer being electrically connected to the n-side electrode,
the p-side metal pillar being provided on a surface of the p-side interconnect layer on a side opposite to a portion contacting the p-side electrode,
the n-side metal pillar being provided on a surface of the n-side interconnect layer on a side opposite to a portion contacting the n-side electrode.
6. The device of claim 5 , wherein an area of the p-side interconnect layer is greater than the area of the p-side external terminal.
7. The device of claim 5 , wherein an area of the n-side interconnect layer is greater than an area of the n-side electrode.
8. The device of claim 5 , wherein the first via is provided in a plurality and the p-side interconnect layer is connected to the p-side electrode via the plurality of the first vias.
9. The device of claim 5 , wherein the p-side metal pillar is thicker than the p-side interconnect layer.
10. The device of claim 5 , wherein the n-side metal pillar is thicker than the n-side interconnect layer.
11. The device of claim 5 , wherein a distance between the p-side external terminal and the n-side external terminal is greater than a distance between the p-side interconnect layer and the n-side interconnect layer.
12. The device of claim 1 , further comprising a transparent body provided on the first surface, the transparent body being transparent to light emitted from the light emitting layer.
13. The device of claim 12 , wherein the transparent body includes a transparent resin and a phosphor dispersed in the transparent resin.
14. The device of claim 1 , wherein a substrate is not provided on the first surface side, and a transparent body is provided on the first surface side without a substrate being interposed between the transparent body and the semiconductor layer.
15. The device of claim 1 , wherein the semiconductor layer is formed on a substrate, and the substrate is removed from the semiconductor layer.
16. The device of claim 15 , wherein the semiconductor layer is a crystal growth layer using the substrate.
17. The device of claim 1 , wherein the semiconductor layer had been formed on a substrate.
18. The device of claim 1 , wherein the p-side external terminal has an end portion to be connected to a mounting member, and the n-side external terminal has an end portion to be connected to the mounting member.
19. The device of claim 1 , wherein the insulator covers a side surface of the semiconductor layer.