SONOS FPGA architecture having fast data erase and disable feature

1. An FPGA integrated circuit comprising:

a programmable logic core;

a controller;

a configuration memory array including a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, driving a switch transistor coupled to one of a programmable logic element and a programmable interconnect connection of the programmable logic core; and

a tamper detector disposed in the integrated circuit having an output coupled to the controller, the controller configured to cause power to be disconnected from the programmable logic core and to then simultaneously program all of the n-channel SONOS memory transistors and erase all of the p-channel SONOS memory transistors in the configuration memory array in response to a tamper detection signal from the tamper detector.

2. The FPGA integrated circuit of claim 1 wherein the controller is configured to cause power to be disconnected from the programmable logic core by disconnecting V DD from the programmable logic core.

3. The FPGA integrated circuit of claim 1 wherein the controller is configured to cause power to be disconnected from the programmable logic core by disconnecting ground from the programmable logic core.

4. The FPGA integrated circuit of claim 1 wherein the controller is configured to cause power to be re-connected to the programmable logic core after the programming of all of the n-channel SONOS memory transistors and the erasing of all of the p-channel SONOS memory transistors in the configuration memory array.

5. The FPGA integrated circuit of claim 1 wherein the controller is further configured to shift all of the voltage thresholds of the p-channel SONOS memory transistors and the n-channel SONOS memory transistors in a negative direction after simultaneously programming all of the n-channel SONOS memory transistors and erasing all of the p-channel SONOS memory transistors in the configuration memory array.

6. The FPGA integrated circuit of claim 5 wherein the controller is further configured to simultaneously program the n-channel SONOS memory transistor cells and erase the p-channel SONOS memory transistors after shifting all of the voltage thresholds of the p-channel SONOS memory transistors and the n-channel SONOS memory transistors in a negative direction.

7. An FPGA integrated circuit comprising:

a programmable logic core;

a controller;

a configuration memory array including a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, driving a switch transistor coupled to one of a programmable logic element and a programmable interconnect connection of the programmable logic core;

a tamper detector disposed in the integrated circuit having an output coupled to the controller; and

a power control switch disposed between the logic core and one of a source of supply voltage for the logic core and a ground connection for the logic core, the power control switch responsive to the controller for connecting and disconnecting power from the programmable logic core;

the controller configured to disconnect power from the programmable logic core via the power control switch and then simultaneously program all of the n-channel SONOS memory transistors and erase all of the p-channel SONOS memory transistors in the configuration memory array in response to a tamper detection signal from the tamper detector.

8. The FPGA integrated circuit of claim 7 wherein the controller is further configured to reconnect power via the power control switch to the programmable logic core after the programming of all of the n-channel SONOS memory transistors and the erasing of all of the p-channel SONOS memory transistors.

9. The FPGA integrated circuit of claim 7 wherein the power control switch is arranged for connecting and disconnecting V DD from the programmable logic core.

10. The FPGA integrated circuit of claim 7 wherein the power control switch is arranged for connecting and disconnecting ground from the programmable logic core.

11. A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, the method comprising:

detecting tampering with the FPGA;

disconnecting power from the programmable logic core; and

simultaneously programming the n-channel SONOS memory transistors in the SONOS configuration memory cells and erasing the p-channel SONOS memory transistors in the SONOS configuration memory cells.

12. The method of claim 11 , further including re-connecting power to the programmable logic core after the programming of the n-channel SONOS memory transistors and the erasing of the p-channel SONOS memory transistors.

13. The method of claim 11 wherein the disconnecting power from the programmable logic core comprises disconnecting V DD from the programmable logic core.

14. The method of claim 11 wherein the disconnecting power from the programmable logic core comprises disconnecting ground from the programmable logic core.

15. The method of claim 11 wherein the simultaneously programming of the n-channel SONOS memory transistors and erasing of the p-channel SONOS memory transistors in all cells comprise:

simultaneously applying a programming potential between a control gate of the n-channel SONOS memory transistor and both of a source of the n-channel SONOS memory transistor and a semiconductor bulk region containing the n-channel SONOS memory transistor;

applying an erase potential between a control gate of the p-channel SONOS memory transistor and both of a source of the p-channel SONOS memory transistor and a semiconductor bulk region containing the p-channel SONOS memory transistor; and

applying a potential of about 0V to a gate of a switch transistor arranged between a drain of the p-channel SONOS memory transistor and a drain of the n-channel SONOS memory transistor.

16. The method of claim 15 wherein the programming potential and the erase potential are the same potential.

17. The method of claim 11 wherein the simultaneously programming of the n-channel SONOS memory transistors and erasing of the p-channel SONOS memory transistors in all cells comprise:

simultaneously applying a programming potential between a control gate of the n-channel SONOS transistor and both of a source of the n-channel SONOS transistor and a semiconductor bulk region containing the n-channel SONOS memory transistor, applying an erase potential between a control gate of the p-channel SONOS memory transistor and both a source of the p-channel SONOS memory transistor and a semiconductor bulk region containing the p-channel SONOS memory transistor; and

applying a potential of V DD to a gate of a switch transistor arranged between a drain of the p-channel SONOS memory transistor and a drain of the n-channel SONOS memory transistor.

18. The method of claim 11 wherein the programming potential and the erase potential are the same potential.

19. The method of claim 11 further comprising shifting all of the voltage thresholds of the p-channel SONOS memory transistors and the n-channel SONOS memory transistors in a negative direction.

20. The method of claim 19 further comprising, after shifting all of the voltage thresholds of the p-channel SONOS memory transistors and the n-channel SONOS memory transistors in the negative direction, simultaneously programming the n-channel SONOS memory transistors cells and erasing the p-channel SONOS memory transistors.