IP Library Granted Patent US 9,583,505
Granted Patent B2
US 9,583,505 · App. 14/483,521 · Granted Feb 28, 2017

Non-volatile memory device

Inventors: Takashi Ishida (Yokkaichi, JP); Yoshiaki Fukuzumi (Yokkaichi, JP); Takayuki Okada (Kuwana, JP); Masaki Tsuji (Yokkaichi, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/11582H01L27/1157H01L27/11565
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Quick Facts
Patent No.
US 9,583,505
App. No.
14/483,521
Granted
Feb 28, 2017
Kind
B2
Abstract

According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Claims (52)

1. A non-volatile memory device comprising:

first electrodes stacked on an underlying layer;

a second electrode provided on the first electrodes;

a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and including a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode;

a memory film provided between at least one of the first electrodes and the semiconductor layer,

the second portion having a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction; and

a core layer adjacent to the semiconductor layer in the second direction,

wherein the semiconductor layer is provided between the core layer and each of the first electrodes, and between the core layer and the second electrode.

2. The device according to claim 1 , further comprising:

an insulating film provided between the first electrodes, and between one of the first electrodes and the second electrode in the first direction,

wherein the insulating film is different in material from the core layer.

3. The device according to claim 1 , wherein an upper surface of the core layer is located at a level in the first direction between an upper surface of the second electrode and an upper end of the semiconductor layer.

4. The device according to claim 1 , wherein

the second electrode includes electrode layers stacked in the first direction,

wherein part of the second portion adjacent to at least one of the electrode layers has a thickness in the second direction that is thinner than that of the first portion.

5. A non-volatile memory device comprising:

first electrodes stacked on an underlying layer,

a second electrode provided on the first electrodes;

a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and including a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode;

a memory film provided between at least one of the first electrodes and the semiconductor layer;

the second portion having a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction;

a third electrode provided between the underlying layer and the first electrodes;

a conductive layer provided between the underlying layer and the third electrode; and

a wiring provided on the second electrode,

wherein one end of the semiconductor layer is electrically connected to the conductive layer, and

the other end of the semiconductor layer is electrically connected to the wiring.

6. The device according to claim 5 , wherein the memory film extends between the second electrode and the semiconductor layer, and between the third electrode and the semiconductor layer.

7. The device according to claim 5 , wherein the second electrode has a thickness in the first direction thicker than that of each first electrode.

8. The device according to claim 5 , wherein part of the first portion adjacent to the third electrode has a thickness in the second direction thicker than that of the second portion.

9. A non-volatile memory device comprising:

first electrodes stacked on a underlying layer;

a second electrode provided on the first electrodes;

a first semiconductor layer extending in a first direction from the underlying layer to the second electrode;

a second semiconductor layer extending in the first direction, and having a thickness in a second direction perpendicular to the first direction thinner than a thickness in the second direction of the first semiconductor layer, the second semiconductor layer being electrically connected to the first semiconductor layer;

a memory film provided between at least one of the first electrodes and the first semiconductor layer; and

a first core layer adjacent to the second semiconductor layer in the second direction,

wherein the second semiconductor layer includes a portion provided between the first core layer and the second electrode.

10. The device according to claim 9 , further comprising:

a second core layer adjacent to the first semiconductor layer in the second direction.

11. The device according to claim 10 , further comprising:

a third electrode provided between the underlying layer and the first electrodes;

a conductive layer provided between the underlying layer and the third electrode; and

a wiring provided on the second electrode,

wherein the first semiconductor layer is electrically connected to the conductive layer, and

the second semiconductor layer is electrically connected to the wiring.

12. The device according to claim 11 , wherein part of the first semiconductor layer adjacent to the third electrode has a thickness in the second direction thicker than a thickness in the second direction of the second semiconductor layer.

13. The device according to claim 9 , wherein the second semiconductor layer has a lower carrier trap level density than that in the first semiconductor layer.

14. The device according to claim 9 , wherein

the first semiconductor layer is a silicon layer, and

the second semiconductor layer is an oxide semiconductor layer.

15. The device according to claim 9 , further comprising:

a gate insulating film placed between the second semiconductor layer and the second electrode, wherein the gate insulating film is different in material from the memory film.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043355/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2014
From: ISHIDA, TAKASHI; FUKUZUMI, YOSHIAKI; OKADA, TAKAYUKI; TSUJI, MASAKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 034233/0619 →
Continuity (2)
Provisional Application 62008343 · Jun 5, 2014
Related Publication 20150357343A1 · Dec 10, 2015