Three-dimensional memory comprising discrete read/write-voltage generator die
The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (V R /V W -generator) is located on a separate peripheral-circuit die. The V R /V W -generator generates at least a read and/or write voltage to the 3D-array die. A single V R /V W -generator die can support multiple 3D-array dies.
1. A discrete three-dimensional memory (3D-M), comprising:
a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory cells;
a peripheral-circuit die comprising at least a portion of a read/write-voltage generator for providing said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, wherein said portion of said read/write-voltage generator is absent from said 3D-array die;
wherein said peripheral-circuit die comprises fewer back-end layers than said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.
2. The discrete 3D-M according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
3. The discrete 3D-M according to claim 1 , wherein said 3D-M comprises at least one of a memristor, a resistive random-access memory (RRAM or ReRAM), a phase-change memory (PCM), a programmable metallization cell (PMC), and a conductive-bridging random-access memory (CBRAM).
4. The discrete 3D-M according to claim 1 , wherein said read/write-voltage generator comprises a step-up whose output voltage is higher than the voltage supply.
5. The discrete 3D-M according to claim 4 , wherein said step-up comprises at least one of a charge pump and a boost converter.
6. The discrete 3D-M according to claim 1 , wherein said read/write-voltage generator comprises a step-down whose output voltage is lower than the voltage supply.
7. The discrete 3D-M according to claim 6 , wherein said step-down comprises at least one of a low dropout and a buck converter.
8. The discrete 3D-M according to claim 1 , further comprising another 3D-M die, wherein said peripheral-circuit die further comprises at least another portion of another read/write-voltage generator for said another 3D-M die, and said another portion of said another read/write-voltage generator is absent from said another 3D-M die.
9. The discrete 3D-M according to claim 1 , wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card or a solid-state drive.
10. The discrete 3D-M according to claim 1 , wherein the array efficiency of said 3D-array die is larger than 40%.
11. A discrete three-dimensional memory (3D-M), comprising:
a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory cells;
a peripheral-circuit die comprising at least a portion of a read/write-voltage generator for providing said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, wherein said portion of said read/write-voltage generator is absent from said 3D-array die;
wherein said peripheral-circuit die comprises different interconnect materials than said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.
12. The discrete 3D-M according to claim 1 , wherein 3D-array die comprises high-temperature interconnect materials.
13. The discrete 3D-M according to claim 1 , wherein peripheral-circuit die comprises high-speed interconnect materials.
14. The discrete 3D-M according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
15. The discrete 3D-M according to claim 1 , further comprising another 3D-M die, wherein said peripheral-circuit die further comprises at least another portion of another read/write-voltage generator for said another 3D-M die, and said another portion of said another read/write-voltage generator is absent from said another 3D-M die.
16. The discrete 3D-M according to claim 1 , wherein the array efficiency of said 3D-array die is larger than 40%.
17. A discrete three-dimensional memory (3D-M), comprising:
a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory cells;
a peripheral-circuit die comprising at least a portion of a read/write-voltage generator for providing said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, wherein said portion of said read/write-voltage generator is absent from said 3D-array die;
wherein said peripheral-circuit die comprises more substrate interconnect layers than said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.
18. The discrete 3D-M according to claim 17 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
19. The discrete 3D-M according to claim 17 , further comprising another 3D-M die, wherein said peripheral-circuit die further comprises at least another portion of another read/write-voltage generator for said another 3D-M die, and said another portion of said another read/write-voltage generator is absent from said another 3D-M die.
20. The discrete 3D-M according to claim 17 , wherein the array efficiency of said 3D-array die is larger than 40%.