Cascode amplifier
In one embodiment, a cascode amplifier includes an amplifier circuit, a replica circuit, a bias circuit, and a feedback circuit. The amplifier circuit includes a first transistor and a second transistor. The second transistor is cascode-connected to the first transistor. The replica circuit includes a third transistor and a fourth transistor. The third transistor has a control terminal connected to a control terminal of the first transistor. The fourth transistor is cascode-connected to the third transistor. The bias circuit applies a bias voltage to a control terminal of the second transistor and a control terminal of the fourth transistor. The feedback circuit performs a feedback control of a voltage of the control terminal of the third transistor. The feedback circuit reduces the difference between a reference current and a current at a predetermined point of the replica circuit.
1. A cascode amplifier comprising:
an amplifier circuit including a first transistor and a second transistor cascode-connected to the first transistor;
a replica circuit including a third transistor having a control terminal connected to a control terminal of the first transistor, and a fourth transistor cascode-connected to the third transistor;
a bias circuit applying a bias voltage to a control terminal of the second transistor and a control terminal of the fourth transistor; and
a feedback circuit performing a feedback control of a voltage of the control terminal of the third transistor to reduce the difference between a reference current and a current at a predetermined point of the replica circuit,
wherein a ratio of a ratio of a channel width to a channel length of the third transistor to a ratio of a channel width to a channel length of the fourth transistor is equal to a ratio of a ratio of a channel width to a channel length of the first transistor to a ratio of a channel width to a channel length of the second transistor.
2. The cascode amplifier according to claim 1 , further comprising:
a buffer circuit provided at least between the control terminal of the first transistor and the control terminal of the third transistor or between the control terminal of the second transistor and the bias circuit.
3. The cascode amplifier according to claim 1 ,
wherein voltages of output terminals of the first transistor and the third transistor are higher than voltages of the control terminals of the first transistor and the third transistor.
4. The cascode amplifier according to claim 1 ,
further comprising: a temperature coefficient circuit generating the reference current according to at least one of the temperatures of the amplifier circuit and the replica circuit.
5. The cascode amplifier according to claim 1 ,
wherein the bias circuit applies a bias voltage based on a threshold voltage of the second transistor and the fourth transistor to the control terminal of the second transistor and the control terminal of the fourth transistor.
6. The cascode amplifier according to claim 1 , further comprising:
a buffer circuit provided between the control terminal of the first second transistor and the bias circuit,
wherein the buffer circuit includes a fifth transistor having a control terminal applied the reference current, and
a sixth transistor connected to the fifth transistor, the sixth transistor having a control terminal applied the bias voltage, and
the feedback circuit includes a seventh transistor having a control terminal applied the reference current, and
an eighth transistor connected to the seventh transistor, the eighth transistor having a control terminal performing the feedback control to the control terminal of the third transistor.
7. The cascode amplifier according to claim 6 ,
wherein a ratio of a ratio of a channel width to a channel length of the fifth transistor to a ratio of a channel width to a channel length of the sixth transistor is equal to a ratio of a ratio of a channel width to a channel length of the seventh transistor to a ratio of a channel width to a channel length of the eighth transistor.
8. The cascode amplifier according to claim 1 ,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are MOS transistors.
9. A cascode amplifier comprising:
an amplifier circuit including a first transistor and a second transistor cascode-connected to the first transistor;
a replica circuit including a third transistor having a control terminal connected to a control terminal of the first transistor, and a fourth transistor cascode-connected to the third transistor;
a bias circuit applying a bias voltage to a control terminal of the second transistor and a control terminal of the fourth transistor; and
a feedback circuit performing a feedback control of a voltage of the control terminal of the third transistor to reduce the difference between a reference voltage and a voltage at a predetermined point of the replica circuit,
wherein a ratio of a ratio of a channel width to a channel length of the third transistor to a ratio of a channel width to a channel length of the fourth transistor is equal to a ratio of a ratio of a channel width to a channel length of the first transistor to a ratio of a channel width to a channel length of the second transistor.
10. The cascode amplifier according to claim 9 , further comprising:
a buffer circuit provided at least between the control terminal of the first transistor and the control terminal of the third transistor or between the control terminal of the second transistor and the bias circuit.
11. The cascode amplifier according to claim 9 ,
wherein voltages of output terminals of the first transistor and the third transistor are higher than voltages of the control terminals of the first transistor and the third transistor.
12. The cascode amplifier according to claim 9 ,
further comprising: a temperature coefficient circuit generating the reference voltage according to at least one of the temperatures of the amplifier circuit and the replica circuit.
13. The cascode amplifier according to claim 9 ,
wherein the bias circuit applies a bias voltage based on a threshold voltage of the second transistor and the fourth transistor to the control terminal of the second transistor and the control terminal of the fourth transistor.
14. The cascode amplifier according to claim 9 , further comprising:
a buffer circuit provided between the control terminal of the first second transistor and the bias circuit,
wherein the buffer circuit includes a fifth transistor having a control terminal applied the reference voltage, and
a sixth transistor connected to the fifth transistor, the sixth transistor having a control terminal applied the bias voltage, and
the feedback circuit includes a seventh transistor having a control terminal applied the reference voltage, and
an eighth transistor connected to the seventh transistor, the eighth transistor having a control terminal performing the feedback control to the control terminal of the third transistor.
15. The cascode amplifier according to claim 14 ,
wherein a ratio of a ratio of a channel width to a channel length of the fifth transistor to a ratio of a channel width to a channel length of the sixth transistor is equal to a ratio of a ratio of a channel width to a channel length of the seventh transistor to a ratio of a channel width to a channel length of the eighth transistor.
16. The cascode amplifier according to claim 9 ,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are MOS transistors.