Method of fabricating integrated structure for MEMS device and semiconductor device
View Patent ↗A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.
1. A method of fabricating an integrated structure for a MEMS device and a semiconductor device, comprising:
providing a substrate, wherein the integrated structure comprises a MEMS region including a first portion of the substrate and an area directly above the first portion of the substrate, an etch stopping device region including a second portion of the substrate and an area directly above the second portion of the substrate, and a semiconductor device region including a third portion of the substrate and an area directly above the third portion of the substrate, the MEMS region is separated from the semiconductor device region by the etch stopping device region, a transistor is disposed on the substrate in the semiconductor device region, and a first MEMS component is disposed on the substrate in the MEMS region;
performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers;
forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in the etch stopping device region;
forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region;
forming a top conductive layer on the first dielectric layers to electrically connect to the conductive plug and the conductive layer in the first dielectric layers;
forming a passivation layer to cover the top conductive layer but not covering the second MEMS component; and
performing an etching process to remove the third dielectric layers in the MEMS region.
2. The method of claim 1 , wherein the etch stopping device is formed simultaneously with the at least a conductive plug or the at least a conductive layer when performing the interconnect process.
3. The method of claim 2 , wherein the interconnect process comprises a damascene process or a dual damascene process.
4. The method of claim 1 , wherein the etch stopping device comprises a plurality of pillared etch-resistant material plugs arranged in a plurality of rows.
5. The method of claim 4 , wherein the etch stopping device further comprises an etch resistant material layer stacked with the pillared etch-resistant material plugs.
6. The method of claim 1 , wherein the etch stopping device comprises at least a wall-shaped etch-resistant material plug.
7. The method of claim 6 , wherein the etch stopping device further comprises an etch resistant material layer stacked with the at least a wall-shaped etch-resistant material plug.
8. The method of claim 1 , wherein the at least a second MEMS component and one of the at least a conductive plug and the at least a conductive layer are formed simultaneously when performing the interconnect process.
9. The method of claim 1 , wherein the etching process comprises a wet etching or a vapor etching.
10. The method of claim 1 , wherein the second MEMS component not directly contacting the first MEMS component.