Addressless merge command with data item identifier
An addressless merge command includes an identifier of an item of data, and a reference value, but no address. A first part of the item is stored in a first place. A second part is stored in a second place. To move the first part so that the first and second parts are merged, the command is sent across a bus to a device. The device translates the identifier into a first address ADR1, and uses ADR1 to read the first part. Stored in or with the first part is a second address ADR2 indicating where the second part is stored. The device extracts ADR2, and uses ADR1 and ADR2 to issue bus commands. Each bus command causes a piece of the first part to be moved. When the entire first part has been moved, the device returns the reference value to indicate that the merge command has been completed.
1. A method comprising:
(a) maintaining Packet Portion Identifier (PPI) to memory address translation information in a device;
(b) receiving a merge command onto the device from a bus, wherein the merge command includes a PPI and a reference value, wherein the merge command includes no address;
(c) using the PPI to read a first portion of a packet from a first memory and to cause the first portion of the packet to be written into a second memory where a second portion of the packet is stored so that both the first portion and the second portion are stored in substantially contiguous memory locations in the second memory; and
(d) outputting the reference value from the device onto the bus, wherein (a) through (d) are performed by the device.
2. The method of claim 1 , wherein the bus is a Command/Push/Pull (CPP) bus, wherein the CPP bus has a set of command conductors, a set of pull-id conductors, and a set of data conductors, wherein the merge command in (b) is received onto the device via the set of command conductors, and wherein the reference value is output from the device in (d) via the set of data conductors.
3. The method of claim 1 , wherein (c) involves:
(c1) using the PPI to read an ingress packet descriptor from the first memory, wherein the ingress packet descriptor is stored in the first memory in association with the first portion of the packet, and wherein the ingress packet descriptor includes a memory address; and
(c2) using the memory address to write the first portion of the packet into the second memory so that both the first portion and the second portion are stored in the substantially contiguous memory locations in the second memory.
4. The method of claim 3 , wherein (c2) involves writing the first portion of the packet into the second memory so that the ingress packet descriptor is stored between the first portion of the packet and the second portion of the packet in the second memory.
5. The method of claim 3 , wherein (c2) involves writing the first portion of the packet into the second memory so that the ingress packet descriptor is not stored between the first portion of the packet and the second portion of the packet in the second memory.
6. The method of claim 1 , wherein (c) involves:
(c1) using the PPI to memory address translation information to obtain a first memory address;
(c2) using the first memory address to read the first portion of the packet from the first memory, wherein the first portion of the packet is stored in association with an ingress packet descriptor, wherein the ingress packet descriptor includes a second memory address; and
(c3) using the second memory address to write the first portion of the packet into the second memory so that both the first portion and the second portion are stored in the substantially contiguous memory locations in the second memory.
7. The method of claim 1 , wherein the device causes the first portion of the packet to be written into the second memory in (c) by outputting at least one write command onto the bus.
8. The method of claim 1 , wherein the device causes the first portion of the packet to be written into the second memory in (c) by outputting a plurality of write commands onto the bus so that the commands are communicated to another device, and wherein the device for each of the write commands receives in response a pull-id bus transaction value from the other device via the bus.
9. The method of claim 8 , wherein one of the pull-id bus transaction values is the last pull-id bus transaction value, and wherein the device outputs the reference value in (d) in response to receiving the last pull-id bus transaction value.
10. The method of claim 1 , wherein the device comprises a state machine, and wherein the device includes no processor that fetches and executes processor-executable instructions.
11. The method of claim 1 , further comprising:
(e) receiving a PPI allocation request onto the device from the bus; and
(f) allocating the PPI in response to the receiving of the PPI allocation request in (e), wherein the device performs the allocating of (f), and wherein (e) and (f) occur prior to the receiving of the merge command in (b).
12. The method of claim 1 , wherein the device and the first memory are parts of an integrated circuit, and wherein the second memory is external to the integrated circuit.
13. The method of claim 1 , wherein the device and the bus are parts of an integrated circuit, wherein the integrated circuit further comprises a plurality of bus-coupled devices, and wherein the merge command received in (b) is communicated from one of the bus-coupled devices across the bus to the device.
14. The method of claim 13 , wherein the integrated circuit comprises a plurality of identical packet engine circuits, and wherein the device that receives the merge command in (b) is one of the packet engine circuits.
15. The method of claim 1 , wherein the device and the bus are parts of an integrated circuit, wherein the device is a packet engine circuit that maintains a number of PPIs, the method further comprising:
(e) maintaining an indication of whether each of the PPIs is currently allocated, wherein (e) is performed by the device.
16. The method of claim 1 , wherein the device and the bus are parts of an integrated circuit, wherein the device is a packet engine circuit that maintains a number of PPIs, the method further comprising:
(e) maintaining an indication of an owner device for each of the PPIs, wherein the owner device is a device to which the PPI is currently allocated, wherein (e) is performed by the device.
17. The method of claim 1 , wherein the device and the bus are parts of an integrated circuit, wherein the device is a packet engine circuit that maintains a number of PPIs, the method further comprising:
(e) maintaining, for each of the PPIs, an indication of a size of a packet portion, wherein (e) is performed by the device.
18. The method of claim 1 , wherein the device and the bus are parts of an integrated circuit, wherein the device is a packet engine circuit that includes an arbiter, the method further comprising:
(e) using the arbiter to arbitrate between multiple requests, wherein one of the multiple requests is a PPI allocation request, wherein (e) is performed by the device.
19. The method of claim 1 , further comprising:
(e) receiving a PPI allocation request onto the device from the bus; and
(f) outputting a PPI allocation response from the device and onto the bus, and wherein the PPI allocation response indicates a PPI that was allocated and also indicates a number of credits.
20. An apparatus comprising:
a first memory;
a bus; and
means for: 1) receiving a merge command from the bus, wherein the merge command includes a Packet Portion Identifier (PPI) and a reference value, wherein the merge command includes no address, 2) in response to the receiving of the merge command using the PPI to read a first portion of a packet from the first memory and to cause the first portion of the packet to be written into a second memory where a second portion of the packet is stored so that both the first portion and the second portion are stored in substantially contiguous memory locations in the second memory, 3) outputting the reference value onto the bus.
21. The apparatus of claim 20 , wherein the apparatus is an integrated circuit, wherein the bus is a Command/Push/Pull (CPP) bus, wherein the CPP bus has a set of command conductors, a set of pull-id conductors, and a set of data conductors, wherein the second memory is a memory external to the integrated circuit, wherein the merge command is received onto the means via the command conductors of the CPP bus, and wherein the reference value is output from the means onto the data conductors of the CPP bus.
22. The apparatus of claim 20 , wherein the means uses the PPI to read the first portion of the packet and to cause the first portion of the packet to be written into the second memory by:
using the PPI to read an ingress packet descriptor from the first memory, wherein the ingress packet descriptor is stored in the first memory in association with the first portion of the packet, and wherein the ingress packet descriptor includes a memory address; and
using the memory address to write the first portion of the packet into the second memory so that both the first portion and the second portion are stored in the substantially contiguous memory locations in the second memory.
23. The apparatus of claim 22 , wherein the means causes the first portion of the packet to be written into the second memory by:
outputting a plurality of write commands onto the bus such that a carrying out of each write command causes a corresponding amount of the first portion to be written into the second memory.
24. The apparatus of claim 22 , wherein the means is also for:
maintaining PPI to memory address translation information;
receiving PPI allocation requests from the bus; and
allocating PPIs in response to the PPI allocation requests.
25. An apparatus comprising:
a second memory;
a Command/Push/Pull (CPP) bus, wherein the CPP bus includes a set of command conductors, a set of pull-id conductors, and a set of data conductors; and
a device comprising a first memory, a Packet Portion Identifier (PPI) to memory address translation circuit, a CPP target interface and a CPP bus master interface, wherein the CPP target interface receives a CPP merge command from the command conductors of the CPP bus via the CPP target interface, wherein the CPP merge command includes a PPI and a reference value, wherein the CPP merge command includes no address from which to read data and includes no address where the data is to be written, wherein the device in response to receiving the CPP merge command uses the PPI and its PPI to memory address translation circuit to read a first portion of a packet from the first memory, wherein the device uses its CPP master interface to cause the first portion of the packet to be written into the second memory where a second portion of the packet is stored so that both the first portion and the second portion are stored in substantially contiguous memory locations in the second memory, and wherein the device uses its CPP target interface to output the reference value onto the data conductors of the CPP bus, wherein the device comprises no processor that fetches and executes processor-executable instructions.
26. An apparatus comprising:
a first memory;
a second memory;
a bus; and
means for: 1) receiving a merge command from the bus, wherein the merge command includes an item identifier and a reference value, wherein the merge command includes no address, 2) in response to the receiving of the merge command using the item identifier to obtain a first address, 3) using the first address to read a first portion of an item from the first memory, wherein the first portion of the item includes a second address, wherein the second address identifies where a second portion of the item is stored in the second memory, 4) using the first address and the second address to cause the first portion of the item to be moved across the bus and to be stored into the second memory so that both the first portion and the second portion are stored in substantially contiguous memory locations in the second memory, 5) outputting the reference value onto the bus, wherein the means includes no processor that fetches and executes processor-executable instructions.
27. The apparatus of claim 26 , wherein the means is also for: 6) allocating the item identifier to the item, wherein the allocating occurs before the receiving of the merge command from the bus, and 7) deallocating the item identifier, wherein the deallocating occurs after the reference value is output onto the bus.