IP Library Granted Patent US 9,275,863
Granted Patent B2
US 9,275,863 · App. 14/492,382 · Granted Mar 1, 2016

Method of fabricating semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,275,863
App. No.
14/492,382
Granted
Mar 1, 2016
Kind
B2
Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims (13)

1. A method of manufacturing a semiconductor device including a MISFET, comprising steps of:

(a) forming a first trench in a semiconductor substrate, the first trench including a first portion and a second portion arranged near a top surface of the semiconductor substrate rather than the first portion such that the second portion has a sloping shape rather than first portion;

(b) forming a gate insulating film of the MISFET over the semiconductor substrate including the first trench;

(c) forming a gate electrode of the MISFET over the gate insulating film in order to be embedded in the first trench;

(d) after the step (c), recessing the gate electrode such that an upper surface of the gate electrode is arranged at a position lower than the second portion;

(e) after the step (d), recessing the gate insulating film such that an upper surface of the gate insulating film is arranged at a position lower than the second portion; and

(f) after the step (e), forming a first insulating film over the gate electrode, the gate insulating film, the second portion and the top surface of the semiconductor substrate.

2. The method of manufacturing a semiconductor device according to the claim 1 ,

wherein, after the step (e), the gate electrode and the gate insulating film are not formed on the second portion.

3. The method of manufacturing a semiconductor device according to the claim 1 ,

wherein the gate insulating film includes a first gate insulating film formed on the first trench and a second gate insulating film formed between the first gate insulating film and the gate electrode,

wherein the first gate insulating film is formed by a thermal oxidation method, and

wherein the second gate insulating film is formed by a CVD method.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2016
From: HITACHI ULSI SYSTEMS CO., LTD.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 038241/0507 →