Memory tracking scheme

1. A tracking circuit for a memory, comprising:

a tracking cell;

a tracking word line connected to the tracking cell;

a tracking bit line connected to the tracking cell; and

a voltage generator connected to a tracking cell power supply node and configured to provide a variable tracking cell power supply voltage to the tracking cell based on a control signal, wherein the variable tracking cell power supply voltage comprises a plurality of selectable operational voltages.

2. The tracking circuit of claim 1 , further comprising a control circuit connected to the tracking bit line, wherein the control circuit generates the control signal.

3. The tracking circuit of claim 2 , wherein the control signal is generated based on a response time of the tracking bit line.

4. The tracking circuit of claim 2 , wherein the control signal controls an access timing of the memory.

5. The tracking circuit of claim 1 , wherein the tracking word line is connected to a first plurality of loading memory cells.

6. The tracking circuit of claim 5 , wherein the tracking bit line is connected to a second plurality of loading memory cells.

7. The tracking circuit of claim 1 , wherein the variable tracking cell power supply voltage is an operational voltage equal to or less than a high power supply voltage provided to the memory.

8. The tracking circuit of claim 1 , wherein the tracking cell comprises a PMOS transistor, and a substrate of the PMOS transistor is coupled to the variable tracking cell power supply voltage.

9. The tracking circuit of claim 1 , wherein the tracking cell comprises a PMOS transistor, and a substrate of the PMOS transistor is coupled to a high power supply voltage provided to the memory.

10. A method, comprising:

determining a tracking cell power supply voltage for a tracking cell in a memory;

generating, using a voltage generator, a variable tracking cell power supply voltage, the variable tracking cell power supply voltage selected from a plurality of operational voltages;

providing the variable tracking cell power supply voltage to the tracking cell via a tracking cell power supply node; and

controlling, using a control circuit, a memory access timing based on a response time of a tracking bit line, wherein the tracking bit line is connected to the tracking cell.

11. The method of claim 10 , further comprising the voltage generator generating the variable tracking cell power supply voltage based on a control signal.

12. The method of claim 11 , further comprising generating the control signal, wherein the control circuit is connected to the tracking bit line.

13. The method of claim 10 , further comprising using a first plurality of loading memory cells to provide a loading emulation for a tracking word line connected to the first plurality of loading memory cells and the tracking cell.

14. The method of claim 13 , further comprising using a second plurality of loading memory cells to provide a loading emulation for a tracking bit line connected to the second plurality of loading memory cells.

15. The method of claim 10 , wherein the tracking cell power supply voltage is an operational voltage equal to or less than a high power supply voltage provided to the memory.

16. The method of claim 10 , further comprising coupling a substrate of a PMOS transistor in the tracking cell to the tracking cell power supply voltage.

17. The method of claim 10 , further comprising coupling a substrate of a PMOS transistor in the tracking cell to a high power supply voltage provided to the memory.

18. A tracking circuit for a memory, comprising:

a tracking cell;

a tracking word line, wherein the tracking word line is connected to the tracking cell and a first plurality of loading memory cells;

a tracking bit line, wherein the tracking bit line is connected to the tracking cell and a second plurality of loading memory cells;

a control circuit connected to the tracking bit line, wherein the control circuit generates a control signal; and

a voltage generator configured to provide a variable tracking cell power supply voltage to the tracking cell, via a variable tracking cell power supply node, based on the control signal, the variable tracking cell power supply voltage comprising one of a plurality of selectable operational voltages.

19. The tracking circuit of claim 18 , wherein the control signal is generated based on a response time of the tracking bit line.

20. The tracking circuit of claim 18 , wherein the control signal controls an access timing of the memory.