Integrated circuit with plural comparators receiving expected data and mask data from different pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
1. An integrated circuit comprising:
A. input pads and output pads;
B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the core circuitry including a first core output coupled to a first output pad, and the core circuitry including a second core output coupled to a second output pad;
C. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first output pad, a mask data input coupled to a third output pad, a compare strobe input coupled to a compare strobe lead, a scan data input, a scan data output, and a scan control input coupled to a scan control lead; and
D. second comparator circuitry having an input coupled to the second core output, an expected data input coupled to the second output pad, a mask data input coupled to a fourth output pad, a compare strobe input coupled to the compare strobe lead, a scan data input coupled to the scan data output of the first comparator circuitry, a scan data output, and a scan control input coupled to the scan control lead.
2. The integrated circuit of claim 1 in which the scan data input of the first comparator circuitry is coupled to an input pad.
3. The integrated circuit of claim 1 in which the scan data output of the second comparator circuitry is coupled to a fifth output pad.