IP Library Granted Patent US 9,385,229
Granted Patent B2
US 9,385,229 · App. 14/495,508 · Granted Jul 5, 2016

Semiconductor device with improved breakdown voltage

Inventors: Hongning Yang (Chandler, AZ); Xin Lin (Phoenix, AZ); Zhihong Zhang (Chandler, AZ); Jiang-Kai Zuo (Chandler, AZ)
Assignee: Freescale Semiconductor, Inc.
H01L29/7824H01L29/66681
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Quick Facts
Patent No.
US 9,385,229
App. No.
14/495,508
Granted
Jul 5, 2016
Kind
B2
Abstract

Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.

Claims (53)

1. A semiconductor device structure comprising:

a layer of dielectric material;

a first region of semiconductor material overlying the layer of dielectric material, the first region having a first conductivity type and a first dopant concentration;

a second region of semiconductor material having a second conductivity type, the second region overlying the first region;

a drift region of semiconductor material having the first conductivity type overlying the second region, at least a portion of the second region residing between the first region and the drift region, the drift region having a second dopant concentration; and

a drain region of semiconductor material having the first conductivity type and a third dopant concentration, wherein:

at least a portion of the drift region resides between the second region and the drain region;

the first dopant concentration is less than or equal to the second dopant concentration;

the third dopant concentration is greater than the second dopant concentration; and

the first region is isolated from the drift region.

2. The semiconductor device structure of claim 1 , wherein the first region abuts the layer of dielectric material.

3. The semiconductor device structure of claim 1 , further comprising a body region of semiconductor material having the second conductivity type, wherein the drift region comprises a lateral drift region that provides a path for current between the drain region and a channel within the body region.

4. The semiconductor device structure of claim 1 , wherein a second portion of the second region underlies the drain region and abuts the first region.

5. The semiconductor device structure of claim 4 , wherein the second portion of the second region resides laterally between portions of the first region.

6. The semiconductor device structure of claim 4 , wherein the first region circumscribes the second portion.

7. The semiconductor device structure of claim 6 , wherein lateral boundaries of the second portion are substantially vertically aligned with lateral boundaries of the drain region.

8. The semiconductor device structure of claim 1 , wherein the first region underlies the drain region.

9. The semiconductor device structure of claim 8 , wherein the first region and the drain region are vertically aligned.

10. The semiconductor device structure of claim 1 , further comprising a third region of semiconductor material having the first conductivity type and the first dopant concentration, wherein:

at least a portion of the second region resides between the third region and the lateral drift region;

at least an interior portion of the second region underlying the drain region resides laterally between the first region and the third region; and

a separation distance between interior boundaries of the first region and the third region is greater than or equal to a width of the drain region.

11. The semiconductor device structure of claim 1 , wherein the first region is floating.

12. The semiconductor device structure of claim 1 , wherein:

a second portion of the second region underlies the drain region; and

a width of the second portion is greater than or equal to a width of the drain region.

13. A semiconductor device structure comprising:

a layer of dielectric material;

a buried region of semiconductor material having a first conductivity type, the buried region overlying and abutting the layer of dielectric material;

a first region of semiconductor material having a second conductivity type overlying the buried region;

a drift region of semiconductor material having the first conductivity type overlying the first region;

a drain region of semiconductor material having the first conductivity type within the drift region, the drain region having a dopant concentration greater than a dopant concentration of the drift region, wherein:

at least a portion of the drift region resides between the drain region and the first region;

at least a portion of the first region resides between the drift region and the buried region; and

the buried region is isolated from the drift region.

14. The semiconductor device structure of claim 13 , wherein a dopant concentration of the buried region is less than the dopant concentration of the drift region.

15. The semiconductor device structure of claim 13 , further comprising a body region of semiconductor material having the second conductivity type, wherein at least a second portion of the first region underlying the body region abuts the layer of dielectric material.

16. The semiconductor device structure of claim 13 , wherein the buried region comprises an annular doped region.

17. The semiconductor device structure of claim 16 , wherein the drift region comprises a lateral drift region overlying the annular doped region.

18. A semiconductor device structure comprising:

a first region of semiconductor material having a first conductivity type and a first dopant concentration;

a second region of semiconductor material having a second conductivity type, the second region overlying the first region;

a drift region of semiconductor material having the first conductivity type overlying the second region, at least a portion of the second region residing between the first region and the drift region, the drift region having a second dopant concentration; and

a drain region of semiconductor material having the first conductivity type and a third dopant concentration, wherein:

at least a portion of the drift region resides between the second region and the drain region;

the first dopant concentration is less than or equal to the second dopant concentration;

the third dopant concentration is greater than the second dopant concentration;

the first region is isolated from the drift region;

a second portion of the second region underlies the drain region and abuts the first region; and

the second portion of the second region resides laterally between portions of the first region.

19. The semiconductor device structure of claim 18 , wherein:

the drift region overlies the portions of the first region; and

the portion of the second region resides vertically between the portions of the first region.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: YANG, HONGNING; LIN, XIN; ZHANG, ZHIHONG; ZUO, JIANG-KAI
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 033813/0478 →
Continuity (1)
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