III-nitride device and FET in a package
View Patent ↗One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
1. A package comprising:
a III-nitride transistor situated on a support surface;
a field effect transistor (FET) stacked atop said III-nitride transistor, such that a drain of said FET resides on and is electrically coupled to a source of said III-nitride transistor;
a first lead electrically coupled to a gate of said FET;
a second lead electrically coupled to a drain on an upper surface of said III-nitride transistor;
a third lead electrically coupled to a source of said FET, wherein said third lead is further mechanically coupled to said support surface.
2. The package of claim 1 , wherein a gate of said III-nitride transistor is coupled to said source of said FET, thereby forming a cascoded switch comprising said III-nitride transistor and said FET.
3. The package of claim 2 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a ribbon.
4. The package of claim 2 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a clip.
5. The package of claim 2 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a wirebond.
6. The package of claim 1 , wherein said FET is a silicon FET.
7. The package of claim 1 , wherein said III-nitride transistor is selected from the group consisting of a GaN FET and a GaN HEMT.
8. The package of claim 1 , wherein said III-nitride transistor comprises a depletion-mode GaN.