IP Library › Granted Patent US 9,111,806
Granted Patent B2
US 9,111,806 · App. 14/496,404 · Granted Aug 18, 2015

Oxide semiconductor, thin film transistor, and display device

Inventors: Shunichi Ito (Atsugi, JP); Toshinari Sasaki (Atsugi, JP); Miyuki Hosoba (Isehara, JP); Junichiro Sakata (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1225H01L27/1248H01L29/45H01L29/7869H01L29/78618
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Quick Facts
Patent No.
US 9,111,806
App. No.
14/496,404
Granted
Aug 18, 2015
Kind
B2
Abstract

An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO 3 (ZnO) m , where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

Claims (104)

1. A display device comprising:

a pixel; and

a driver circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the driver circuit being configured so that:

a first terminal of the first transistor is electrically connected to a fourth wiring, and a second terminal of the first transistor is electrically connected to a third wiring;

a first terminal of the second transistor is electrically connected to a sixth wiring, and a second terminal of the second transistor is electrically connected to the third wiring;

a first terminal of the third transistor is electrically connected to a seventh wiring, a second terminal of the third transistor is electrically connected to a gate electrode of the second transistor, and a gate electrode of the third transistor is electrically connected to the seventh wiring;

a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor;

a first terminal of the fifth transistor is electrically connected to a fifth wiring, a second terminal of the fifth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the fifth transistor is electrically connected to a first wiring;

a first terminal of the sixth transistor is electrically connected to the sixth wiring, a second terminal of the sixth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;

a first terminal of the seventh transistor is electrically connected to the sixth wiring, a second terminal of the seventh transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the seventh transistor is electrically connected to a second wiring; and

a first terminal of the eighth transistor is electrically connected to the sixth wiring, a second terminal of the eighth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the eighth transistor is electrically connected to the first wiring,

wherein one of the first to the eighth transistors comprises:

an oxide semiconductor layer;

a first oxide insulating layer and a second oxide insulating layer sandwiching the oxide semiconductor layer, each of the first oxide insulating layer and the second oxide insulating layer being in direct contact with the oxide semiconductor layer; and

a first nitride insulating layer and a second nitride insulating layer sandwiching a stack formed of the oxide semiconductor layer, the first oxide insulating layer, and the second oxide insulating layer.

2. A display device comprising:

a pixel; and

a driver circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the driver circuit being configured so that:

a first terminal of the first transistor is electrically connected to a fourth wiring, and a second terminal of the first transistor is electrically connected to a third wiring;

a first terminal of the second transistor is electrically connected to a sixth wiring, and a second terminal of the second transistor is electrically connected to the third wiring;

a first terminal of the third transistor is electrically connected to a seventh wiring, a second terminal of the third transistor is electrically connected to a gate electrode of the second transistor, and a gate electrode of the third transistor is electrically connected to the seventh wiring;

a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor;

a first terminal of the fifth transistor is electrically connected to a fifth wiring, a second terminal of the fifth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the fifth transistor is electrically connected to a first wiring;

a first terminal of the sixth transistor is electrically connected to the sixth wiring, a second terminal of the sixth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;

a first terminal of the seventh transistor is electrically connected to the sixth wiring, a second terminal of the seventh transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the seventh transistor is electrically connected to a second wiring; and

a first terminal of the eighth transistor is electrically connected to the sixth wiring, a second terminal of the eighth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the eighth transistor is electrically connected to the first wiring,

wherein one of the first to the eighth transistors comprises:

an oxide semiconductor layer;

a first silicon oxide layer and a second silicon oxide layer sandwiching the oxide semiconductor layer, each of the first silicon oxide layer and the second silicon oxide layer being in direct contact with the oxide semiconductor layer; and

a first silicon nitride layer and a second silicon nitride layer sandwiching a stack formed of the oxide semiconductor layer, the first silicon oxide layer, and the second silicon oxide layer.

3. A display device comprising:

a pixel; and

a driver circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the driver circuit being configured so that:

a first terminal of the first transistor is electrically connected to a fourth wiring, and a second terminal of the first transistor is electrically connected to a third wiring;

a first terminal of the second transistor is electrically connected to a sixth wiring, and a second terminal of the second transistor is electrically connected to the third wiring;

a first terminal of the third transistor is electrically connected to a seventh wiring, a second terminal of the third transistor is electrically connected to a gate electrode of the second transistor, and a gate electrode of the third transistor is electrically connected to the seventh wiring;

a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor;

a first terminal of the fifth transistor is electrically connected to a fifth wiring, a second terminal of the fifth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the fifth transistor is electrically connected to a first wiring;

a first terminal of the sixth transistor is electrically connected to the sixth wiring, a second terminal of the sixth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;

a first terminal of the seventh transistor is electrically connected to the sixth wiring, a second terminal of the seventh transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the seventh transistor is electrically connected to a second wiring; and

a first terminal of the eighth transistor is electrically connected to the sixth wiring, a second terminal of the eighth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the eighth transistor is electrically connected to the first wiring,

wherein one of the first to the eighth transistors comprises:

an oxide semiconductor layer;

a first silicon oxide layer and a second silicon oxide layer sandwiching the oxide semiconductor layer, each of the first silicon oxide layer and the second silicon oxide layer being in direct contact with the oxide semiconductor layer; and

a first silicon nitride layer and a second silicon nitride layer sandwiching a stack formed of the oxide semiconductor layer, the first silicon oxide layer, and the second silicon oxide layer,

wherein the first silicon nitride layer and the second silicon nitride layer are in direct contact with the first silicon oxide layer and the second silicon oxide layer, respectively.

4. The display device according to claim 1 , the one of the first to the eighth transistors further comprising:

a gate electrode; and

a source electrode and a drain electrode each in direct contact with the oxide semiconductor layer,

wherein the first oxide insulating layer and the first nitride insulating layer are interposed between the gate electrode and the oxide semiconductor layer.

5. The display device according to claim 2 , the one of the first to the eighth transistors further comprising:

a gate electrode; and

a source electrode and a drain electrode each in direct contact with the oxide semiconductor layer,

wherein the first silicon oxide layer and the first silicon nitride layer are each interposed between the gate electrode and the oxide semiconductor layer.

6. The display device according to claim 3 , the one of the first to the eighth transistors further comprising:

a gate electrode; and

a source electrode and a drain electrode each in direct contact with the oxide semiconductor layer,

wherein the first silicon oxide layer and the first silicon nitride layer are each interposed between the gate electrode and the oxide semiconductor layer.

7. The display device according to claim 1 , the one of the first to the eighth transistors further comprising:

a gate electrode; and

a source electrode and a drain electrode each in direct contact with the oxide semiconductor layer,

wherein the first oxide insulating layer and the first nitride insulating layer are interposed between the gate electrode and the oxide semiconductor layer, and

wherein the first nitride insulating layer and the second nitride insulating layer are in direct contact with the first oxide insulating layer and the second oxide insulating layer, respectively.

8. The display device according to claim 2 , the one of the first to the eighth transistors further comprising:

a gate electrode; and

a source electrode and a drain electrode each in direct contact with the oxide semiconductor layer,

wherein the first silicon oxide layer and the first silicon nitride layer are each interposed between the gate electrode and the oxide semiconductor layer, and

wherein the first silicon nitride layer and the second silicon nitride layer are in direct contact with the first silicon oxide layer and the second silicon oxide layer, respectively.

9. The display device according to claim 3 , the one of the first to the eighth transistors further comprising:

a gate electrode; and

a source electrode and a drain electrode each in direct contact with the oxide semiconductor layer,

wherein the first silicon oxide layer and the first silicon nitride layer are each interposed between the gate electrode and the oxide semiconductor layer, and

wherein the first silicon nitride layer and the second silicon nitride layer are in direct contact with the first silicon oxide layer and the second silicon oxide layer, respectively.

10. The display device according to claim 1 ,

wherein the first wiring and the fifth wiring are distinct from each other.

11. The display device according to claim 2 ,

wherein the first wiring and the fifth wiring are distinct from each other.

12. The display device according to claim 3 ,

wherein the first wiring and the fifth wiring are distinct from each other.

13. The display device according to claim 1 ,

wherein the first to the eighth transistors have a same structure.

14. The display device according to claim 2 ,

wherein the first to the eighth transistors have a same structure.

15. The display device according to claim 3 ,

wherein the first to the eighth transistors have a same structure.

16. The display device according to claim 1 ,

wherein the oxide semiconductor layer has an amorphous structure.

17. The display device according to claim 2 ,

wherein the oxide semiconductor layer has an amorphous structure.

18. The display device according to claim 3 ,

wherein the oxide semiconductor layer has an amorphous structure.

19. A semiconductor device comprising:

an oxide semiconductor layer;

a first silicon oxide layer and a second silicon oxide layer sandwiching the oxide semiconductor layer, each of the first silicon oxide layer and the second silicon oxide layer being in direct contact with the oxide semiconductor layer; and

a first silicon nitride layer and a second silicon nitride layer sandwiching a stack formed of the oxide semiconductor layer, the first silicon oxide layer, and the second silicon oxide layer.

20. The semiconductor device according to claim 19 , further comprising:

a gate electrode; and

a source electrode and a drain electrode each in direct contact with the oxide semiconductor layer,

wherein the first silicon oxide layer and the first silicon nitride layer are interposed between the gate electrode and the oxide semiconductor layer.

21. The semiconductor device according to claim 19 , further comprising:

a gate electrode; and

a source electrode and a drain electrode each in direct contact with the oxide semiconductor layer,

wherein the first silicon oxide layer and the first silicon nitride layer are interposed between the gate electrode and the oxide semiconductor layer, and

wherein the first silicon oxide layer and the second silicon oxide layer are in direct contact with the first silicon nitride layer and the second silicon nitride layer, respectively.

Priority Claims (1)
JP 2008-274564 · Oct 24, 2008 · national
Continuity (2)
Continuation 12581187 · Oct 19, 2009
Related Publication 20150048364A1 · Feb 19, 2015