Semiconductor device and power conversion device
A switching device includes a power semiconductor chip, and a drive circuit which drives the power semiconductor chip. In the power semiconductor chip, a path through which a main current flows is connected to a first source terminal, and a ground terminal of the drive circuit is connected to a second source terminal of the power semiconductor chip. As a result, a gate drive path is separated from the path through which the main current flows, and therefore, the influence of induced electromotive force which is generated due to source parasitic inductance, on a gate-source voltage, is reduced.
1. A semiconductor device comprising a power semiconductor chip, wherein:
the power semiconductor chip includes:
a substrate,
a semiconductor multilayer arrangement formed on the substrate,
a source electrode and a drain electrode formed on the semiconductor multilayer arrangement with a space between the source electrode and the drain electrode,
a gate electrode formed between the source electrode and the drain electrode,
a drain lead trace, a first source lead trace, and a second source lead trace, and
a first terminal, a second terminal, a third terminal, and a fourth terminal, and
the gate electrode is connected to the first terminal,
the drain electrode and the second terminal are connected together through the drain lead trace,
the source electrode and the third terminal are connected together through the first source lead trace,
the source electrode and the fourth terminal are connected together through the second source lead trace, and
the second terminal and the third terminal are configured to cause a main current to flow between the second terminal and the third terminal.
2. The semiconductor device of claim 1 , wherein the second source lead trace is formed between the first source lead trace and the drain lead trace.
3. The semiconductor device of claim 1 , wherein the drain lead trace, the first source lead trace, and the second source lead trace are each an elongated trace extending in a horizontal or vertical direction.
4. The semiconductor device of claim 1 , wherein the trace width of the second source lead trace is smaller than the trace width of the drain lead trace or the first source lead trace.
5. The semiconductor device of claim 1 , wherein the second source lead trace is formed in the same layer in which the source electrode is formed.
6. The semiconductor device of claim 1 , wherein the second source lead trace is formed on an inactive region.
7. The semiconductor device of claim 1 , wherein the gate electrode and the source electrode are each in the shape of a comb.
8. The semiconductor device of claim 1 , wherein the second source lead trace and the fourth terminal are connected together by an upper-layer trace.
9. The semiconductor device of claim 1 , wherein the semiconductor multilayer arrangement is formed of a nitride semiconductor.
10. The semiconductor device of claim 9 , wherein the power semiconductor chip further includes a p-type semiconductor layer formed between the gate electrode and the semiconductor multilayer arrangement.
11. A power conversion device comprising the semiconductor device of claim 1 , wherein:
the power semiconductor chip comprises a half-bridge configuration including a high-side switch and a low-side switch, and
the high-side switch includes the gate electrode, the source electrode and the drain electrode.
12. The power conversion device of claim 11 , wherein:
the power semiconductor chip further includes a drive circuit formed between the first terminal and the gate electrode, and
the drive circuit has a ground terminal connected to the fourth terminal.
13. The power conversion device of claim 12 , wherein the drive circuit includes any of a MOSFET, a JFET, and an HFET.