Single operation array index computation

1. A processor for adjusting an index, wherein the index is used in a process to identify a location of an element within an array, the processor comprising:

a shift circuit configured to perform a single operation that:

performs an adjustment of a first parameter of the index to match a parameter of an array address; and

performs an adjustment of a second parameter of the index to match a parameter of the array element.

2. The processor of claim 1 , wherein:

said array address comprises an identification of a start location of the array;

said first parameter comprises a size of the index;

said second parameter comprises a value of the index;

said parameter of the array address comprises a size of the array address; and

said parameter of the array element corresponds to a size of the array element.

3. The processor of claim 2 , wherein said adjustment of said first parameter of the index comprises a sign extension of said first parameter.

4. The processor of claim 3 , wherein:

said adjustment of said first parameter of the index comprises a pseudo shift; and

said adjustment of said second parameter of the index comprises a shift.

5. The processor of claim 4 wherein:

said shift circuit comprises a data path;

said data path comprises multiple levels; and

said multiple levels perform said pseudo shift and said shift.

6. The processor of claim 5 , wherein:

said pseudo shift comprises replicating said sign of said value of said index; and

said shift comprises shifting bits of the index.

7. The processor of claim 4 , wherein:

said shift circuit comprises a selection logic; and

said selection logic instructs said data path to perform said pseudo shift and said shift.

8. The processor of claim 7 , wherein:

said pseudo shift comprises replicating said sign of said value of said index by an amount corresponding to a size of the array address; and

said shift comprises shifting said second parameter by an amount corresponding to said parameter of the array element.

9. The processor of claim 1 wherein said adjustment of said first parameter of said index or said adjustment of said second parameter of said index comprises performing at least one of a shift and a rotate operation when an input size of said at least one of a shift and a rotate corresponds to an output size of said at least one of a shift and a rotate.

10. The processor of claim 9 wherein said shift circuit is further configured to select an unmodified input value as another value into which to insert said at least one of a shifted and a rotated value.

11. The processor of claim 1 wherein:

said shift circuit comprises a rotate-and-insert logic having a rotate function and an insert function; and

said insert function is configured to comprises inserting a rotated index value into another value;

wherein said another value corresponds an output of a sign extended index value.

12. The processor of claim 1 wherein:

said shift circuit comprises a shift-and-insert logic having a shift function and an insert function; and

said insert function is configured to comprise inserting a shifted index value into another value;

wherein said another value corresponds an output of a sign extended index value.

13. A computer program product for adjusting an index, wherein the index is used in a process to identify a location of an element within an array, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions readable by a processor circuit to cause the processor circuit to perform a method, the method comprising:

performing, by said processor circuit, a single operation that:

performs an adjustment of a first parameter of the index to match a parameter of an array address; and

performs an adjustment of a second parameter of the index to match a parameter of the array element.

14. The computer program product of claim 13 , wherein:

said array address comprises an identification of a start location of the array;

said first parameter comprises a size of the index;

said second parameter comprises a value of the index;

said parameter of the array address comprises a size of the array address; and

said parameter of the array element corresponds to a size of the array element.

15. The computer program product of claim 14 , wherein said adjustment of said first parameter of the index comprises a sign extension of said first parameter.

16. The computer program of claim 14 , wherein said adjustment of said second parameter of the index comprises shifting said second parameter by an amount corresponding to said parameter of the array element.