IP Library Granted Patent US 9,337,266
Granted Patent B2
US 9,337,266 · App. 14/502,804 · Granted May 10, 2016

Methods and apparatuses including an active area of a tap intersected by a boundary of a well

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,337,266
App. No.
14/502,804
Granted
May 10, 2016
Kind
B2
Abstract

Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.

Claims (17)

1. An apparatus comprising:

a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity; and

a tap to the well, wherein a boundary of the well between the well and the semiconductor structure intersects an active area of the tap such that the boundary occurs within the active area and the boundary separates a first doped area of the active area from a second doped area of the active area, wherein the second doped area is more heavily doped than the first doped area with a same conductivity dopant.

2. The apparatus of claim 1 , wherein the tap straddles the boundary of the well.

3. The apparatus of claim 1 , further comprising a contact coupled to the active area of the tap, wherein the contact is over the well.

4. The apparatus of claim 1 , wherein the second doped area is implanted with a n+ dopant and the first doped area is implanted with a n− dopant.

5. The apparatus of claim 1 , wherein a p-n junction formed by the well and the semiconductor structure has a substantially vertical junction and a substantially horizontal junction.

6. The apparatus of claim 1 , wherein the active area of the tap is continuous along the boundary of the well.

7. A method for forming an apparatus, the method comprising:

forming a well having a first type of conductivity within a semiconductor structure having a second type of conductivity; and

forming a tap to the well comprising an active area such that a boundary of the well between the well and the semiconductor structure intersects the active area of the tap wherein the boundary occurs within the active area and the boundary separates a first doped area of the active area from a second doped area of the active area, wherein the second doped area is more heavily doped than the first doped area with a same conductivity dopant.

8. The method of claim 7 , further comprising forming a trench in the semiconductor structure, wherein a portion of the semiconductor structure remains between a side surface of the trench and an edge of the well.

9. The method of claim 8 , further comprising filling the trench with a dielectric material.

10. The method of claim 9 , further comprising implanting an exposed portion of the well with another dopant to form an area that is more heavily doped than a remaining portion of the well.

11. The method of claim 8 , wherein forming the tap comprises implanting the portion of the semiconductor structure that remains between the side surface of the trench and the edge of the well with a dopant.

12. The method of claim 11 , further comprising forming a contact on the area that is more heavily doped than the remaining portion of the well.

13. The method of claim 8 , further comprising implanting a dopant into another portion of the semiconductor structure adjacent to a bottom surface of the trench to form an isolation area.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2014
From: SMITH, MICHAEL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 034267/0734 →