IP Library Granted Patent US 9,865,549
Granted Patent B2
US 9,865,549 · App. 14/505,006 · Granted Jan 9, 2018

Semiconductor device, manufacturing method thereof, and electronic apparatus

Inventor: Takushi Shigetoshi (Kanagawa, JP)
Assignee: Sony Corporation
H01L23/5383H01L21/76898H01L23/481H01L23/528H01L23/5226H01L23/5283H01L23/538H01L27/14634H01L27/14636H01L27/14678H01L27/14641H01L29/0623H01L2224/08145H01L2224/24147H01L2224/80896H01L2224/8203H01L2224/92H01L2924/0002
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Quick Facts
Patent No.
US 9,865,549
App. No.
14/505,006
Granted
Jan 9, 2018
Kind
B2
Abstract

A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.

Claims (36)

1. A semiconductor device comprising:

a first semiconductor substrate including:

a first plurality of wiring layers, each wiring layer of the first plurality of wiring layers including a wire, at least one low-dielectric rate interlayer insulating film layer, and a diffusion barrier film, wherein the first plurality of wiring layers is arranged such that at least one low-dielectric rate interlayer insulating film layer is between each of the wire and the diffusion barrier film and the diffusion barrier film is disposed on each wire of the first plurality of wiring layers;

a guard ring including a wire from each of the first plurality of wiring layers and a plurality of vias arranged in a stacked structure and in contact with a through electrode, wherein each wire from each of the first plurality of wiring layers is electrically connected to a respective via of the plurality of vias, and at least one via of the plurality of vias includes metal material disposed between the diffusion barrier film and the through electrode; and

a second semiconductor substrate including:

a second plurality of wiring layers, each wiring layer of the second plurality of wiring layers including a wire, at least one interlayer insulating film layer, and a diffusion barrier film, wherein the second plurality of wiring layers is arranged such that at least one interlayer insulating film layer is between each of the wire and the diffusion barrier film and each wire of the second plurality of wiring layers is disposed on the diffusion barrier film; and

a pad electrically connected to a wire of a wiring layer of the second plurality of wiring layers,

wherein the through electrode is buried inside the guard ring and electrically connected to the pad.

2. The semiconductor device according to claim 1 ,

wherein of the first and second semiconductor substrates are stacked, and

wherein the first semiconductor substrate is electrically connected to the second semiconductor substrate through the through electrode.

3. The semiconductor device according to claim 2 , wherein a semiconductor substrate including a contact image sensor (CIS) is stacked on the first semiconductor substrate.

4. The semiconductor device according to claim 2 , wherein the first semiconductor substrate includes a signal processing circuit.

5. The semiconductor device according to claim 2 , wherein the first semiconductor substrate includes a contact image sensor (CIS).

6. The semiconductor device according to claim 2 , wherein another semiconductor substrate includes a signal processing circuit.

7. The semiconductor device according to claim 2 , wherein a third semiconductor substrate includes a storage medium circuit.

8. The semiconductor device according to claim 1 , wherein the pad is located within an insulating film of the second semiconductor substrate.

9. An electronic apparatus comprising:

a semiconductor device, the semiconductor device including:

a first semiconductor substrate including:

a first plurality of wiring layers, each wiring layer of the first plurality of wiring layers including a wire, at least one low-dielectric rate interlayer insulating film layer, and a diffusion barrier film, wherein the first plurality of wiring layers is arranged such that at least one low-dielectric rate interlayer insulating film layer is between each of the wire and the diffusion barrier film and the diffusion barrier film is disposed on each wire of the first plurality of wiring layers;

a guard ring including a wire from each of the first plurality of wiring layers and a plurality of vias arranged in a stacked structure and in contact with a through electrode, wherein each wire from each of the first plurality of wiring layers is electrically connected to a respective via of the plurality of vias, and at least one via of the plurality of vias includes metal material disposed between the diffusion barrier film and the through electrode; and

a second semiconductor substrate including:

a second plurality of wiring layers, each wiring layer of the second plurality of wiring layers including a wire, at least one interlayer insulating film layer, and a diffusion barrier film, wherein the second plurality of wiring layers is arranged such that at least one interlayer insulating film layer is between each of the wire and the diffusion barrier film and each wire of the second plurality of wiring layers is disposed on the diffusion barrier film; and

a pad electrically connected to a wire of a wiring layer of the second plurality of wiring layers,

wherein the through electrode is buried inside the guard ring and electrically connected to the pad; and

a lens configured to direct light to an imaging surface of the semiconductor device.

10. The electronic apparatus according to claim 9 , wherein the semiconductor device is a solid-state imaging device, and wherein the semiconductor device further includes:

a signal processing circuit that processes an output signal that is output from the solid-state imaging device; and

an optical system that forms an image on an imaging plane of the solid-state imaging device.

11. The electronic apparatus according to claim 9 ,

wherein of the first and second semiconductor substrates are stacked, and

wherein the first semiconductor substrate is electrically connected to the second semiconductor substrate through the through electrode.

12. The electronic apparatus according to claim 11 , wherein the first semiconductor substrate includes a signal processing circuit.

13. The electronic apparatus according to claim 11 , wherein a third semiconductor substrate includes a storage medium circuit.

14. The semiconductor device according to claim 9 , wherein the pad is located within an insulating film of the second semiconductor substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2014
From: SHIGETOSHI, TAKUSHI
To: SONY CORPORATION
Reel/Frame 033887/0177 →
Priority Claims (1)
JP 2013-211642 · Oct 9, 2013 · national
Continuity (1)
Related Publication 20150097258A1 · Apr 9, 2015