Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
View Patent ↗A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
1. An in process semiconductor device, comprising:
an etch mask above a layer to be etched, the etch mask comprising a plurality of triads of spacers on the outermost surface of the layer to be etched, the triads comprising the first spacer bracketed by second spacers on the surface with each of the spacers within the triad having a different elevational thickness and the second spacers contacting the first spacer, wherein the first spacer has an elevational thickness greater than either of the bracketing second spacers.
2. The in process semiconductor device of claim 1 wherein at least one of the spacers comprises silicon nitride.
3. The in process semiconductor device of claim 1 wherein each of the spacers are formed from one of two different types of materials.
4. The in process semiconductor device of claim 1 wherein the at least two spacers are adjacent spacers comprising different materials.
5. An in process semiconductor device comprising:
an etch mask above a layer to be etched, the etch mask comprising a plurality of groups of five adjacent spacers of the layer to be etched, each group comprising triads of spacers on the outermost surface, the triads comprising the first spacer bracketed by second spacers on the surface with each of the spacers within the triad having a different elevational thickness and the second spacers contacting the first spacer, wherein the first spacer has an elevational thickness greater than either of the bracketing second spacers.
6. The in process semiconductor device of claim 5 wherein all of the spacers are non-planar.
7. The in process semiconductor device of claim 5 wherein at least one of the spacers comprise silicon nitride.
8. The in process semiconductor device of claim 5 wherein each spacer within the group of five spacers has a different elevational thickness.
9. The in process semiconductor device of claim 5 wherein the groups of five spacers are spaced apart from one another.
10. The in process semiconductor device of claim 5 wherein individual spacers within the groups of five spacers contact one another.