Enhanced conduction for p-channel device
A technique for enhancing the conduction of a p-channel device is disclosed. Specifically, a negative charge pump is configured to provide a gate drive voltage to a p-channel device. The negative charge pump creates a negative voltage potential below ground and facilitates increased gate drive for the p-channel device. The gate drive voltage output by the negative charge pump may be selected such that it is optimal for the p-channel device operation.
1. A circuit, comprising:
a p-channel device configured as a switch and having a gate drive voltage while in an on switch state;
a first gate driver that drives the gate voltage of the p-channel device to a negative voltage output by a negative charge pump when an input pin of the circuit comprises a first state while in the on switch state, wherein the first state of the input pin while in the on switch state enables the negative charge pump; and
a second gate driver that drives the gate voltage of the p-channel device to ground when the input pin of the circuit comprises a second state while in the on switch state, wherein the second state of the input pin while in the on switch state disables the negative charge pump;
wherein when enabled the negative charge pump runs from quiescent current and when disabled average quiescent current is zero, wherein the circuit comprises an integrated circuit, wherein the input pin of the integrated circuit receives a signal for enabling and disabling the negative charge pump, and wherein the on switch state is determined by a signal received on a second input pin of the integrated circuit.
2. The circuit of claim 1 , wherein the negative voltage output by the negative charge pump comprises a maximum gate-to-source voltage (V GS ) of the p-channel device below input supply voltage (V IN ).
3. The circuit of claim 1 , wherein the gate drive voltage comprises an optimal gate drive level for the p-channel device.
4. The circuit of claim 1 , wherein the gate drive voltage achieves a prescribed conduction of the p-channel device.
5. The circuit of claim 1 , wherein operation of the p-channel device is not limited to a prescribed voltage range.
6. The circuit of claim 1 , wherein the p-channel device comprises a PMOS (p-channel metal-oxide-semiconductor field-effect transistor) device.
7. The circuit of claim 1 , wherein the p-channel device comprises a power MOSFET (metal-oxide-semiconductor field-effect transistor).
8. The circuit of claim 1 , wherein the switch comprises a load switch.
9. The circuit of claim 1 , wherein the negative charge pump comprises a ring oscillator.
10. A method, comprising:
driving a p-channel device configured as a switch and having a gate drive voltage while in an on switch state using a first gate driver that drives the gate voltage of the p-channel device to a negative voltage output by a negative charge pump when an input pin of an associated circuit comprises a first state while in the on switch state, wherein the first state of the input pin while in the on switch state enables the negative charge pump; and
driving the p-channel device using a second gate driver that drives the gate voltage of the p-channel device to ground when the input pin of the circuit comprises a second state while in the on switch state, wherein the second state of the input pin while in the on switch state disables the negative charge pump;
wherein when enabled the negative charge pump runs from quiescent current and when disabled average quiescent current is zero, wherein the circuit comprises an integrated circuit, wherein the input pin of the integrated circuit receives a signal for enabling and disabling the negative charge pump, and wherein the on switch state is determined by a signal received on a second input pin of the integrated circuit.
11. The method of claim 10 , wherein the negative charge pump comprises a ring oscillator.
12. The method of claim 10 , wherein the negative voltage output by the negative charge pump comprises a maximum gate-to-source voltage (V GS ) of the p-channel device below input supply voltage (V IN ).
13. The method of claim 10 , wherein the gate drive voltage comprises an optimal gate drive level for the p-channel device.
14. The method of claim 10 , wherein the gate drive voltage achieves a prescribed conduction of the p-channel device.
15. The method of claim 10 , wherein operation of the p-channel device is not limited to a prescribed voltage range.
16. The method of claim 10 , wherein the p-channel device comprises a PMOS (p-channel metal-oxide-semiconductor field-effect transistor) device.
17. The method of claim 10 , wherein the p-channel device comprises a power MOSFET (metal-oxide-semiconductor field-effect transistor).
18. The method of claim 10 , wherein the switch comprises a load switch.
19. A non-transitory computer readable storage medium having computer-readable program instructions for:
driving a p-channel device configured as a switch and having a gate drive voltage while in an on switch state using a first gate driver that drives the gate voltage of the p-channel device to a negative voltage output by a negative charge pump when an input pin of an associated circuit comprises a first state while in the on switch state, wherein the first state of the input pin while in the on switch state enables the negative charge pump; and
driving the p-channel device using a second gate driver that drives the gate voltage of the p-channel device to ground when the input pin of the circuit comprises a second state while in the on switch state, wherein the second state of the input pin while in the on switch state disables the negative charge pump;
wherein when enabled the negative charge pump runs from quiescent current and when disabled average quiescent current is zero, wherein the circuit comprises an integrated circuit, wherein the input pin of the integrated circuit receives a signal for enabling and disabling the negative charge pump, and wherein the on switch state is determined by a signal received on a second input pin of the integrated circuit.
20. The computer readable storage medium of claim 19 , wherein the negative voltage output by the negative charge pump comprises a maximum gate-to-source voltage (V GS ) of the p-channel device below input supply voltage (V IN ).
21. The computer readable storage medium of claim 19 , wherein the gate drive voltage comprises an optimal gate drive level for the p-channel device.
22. The computer readable storage medium of claim 19 , wherein the gate drive voltage achieves a prescribed conduction of the p-channel device.
23. The computer readable storage medium of claim 19 , wherein operation of the p-channel device is not limited to a prescribed voltage range.
24. The computer readable storage medium of claim 19 , wherein the p-channel device comprises a PMOS (p-channel metal-oxide-semiconductor field-effect transistor) device.
25. The computer readable storage medium of claim 19 , wherein the p-channel device comprises a power MOSFET (metal-oxide-semiconductor field-effect transistor).
26. The computer readable storage medium of claim 19 , wherein the switch comprises a load switch.
27. The computer readable storage medium of claim 19 , wherein the negative charge pump comprises a ring oscillator.