Power sensing
Improved techniques for sensing and reporting power consumption from a single or multiple power supplies are disclosed. The disclosed techniques comprise integrated circuit solutions for sensing power. In some embodiments, an integrated circuit comprises circuitry for converting source voltage into a pulse-width modulation (PWM) signal and circuitry for modulating the PWM signal with a current sense signal to determine sensed power.
1. An integrated circuit, comprising:
circuitry to convert a source voltage into a pulse-width modulation (PWM) signal, wherein the PWM signal represents the source voltage as a fraction or percentage of a maximum source voltage of a power supply of an associated system and wherein the fraction or percentage comprises an amount of time to ramp from zero to the source voltage divided by an amount of time to ramp from zero to the maximum source voltage; and
a switch controlled by the PWM signal, wherein a current sense signal is applied to a resistor for an amount of time the switch is turned on based on a duty cycle of the PWM signal to determine a sensed power of the associated system, wherein the current sense signal is proportional to a load current drawn by the system by a factor set by a transistor ratio of transistors of the integrated circuit, wherein the sensed power is the same fraction or percentage of a maximum power of the power supply of the associated system, and wherein the integrated circuit does not have a voltage constraint due to silicon process technology but rather senses source voltage and current higher than a process technology of the integrated circuit.
2. The integrated circuit of claim 1 , wherein the source voltage modulates a pulse width of the PWM signal.
3. The integrated circuit of claim 1 , wherein a pulse width of the PWM signal depends on a magnitude of the source voltage.
4. The integrated circuit of claim 1 , wherein the duty cycle of the PWM signal is proportional to the source voltage.
5. The integrated circuit of claim 1 , wherein the duty cycle of the PWM signal is 100% when the source voltage comprises the maximum source voltage.
6. The integrated circuit of claim 1 , wherein the source voltage comprises the maximum source voltage scaled by a ratio comprising the duty cycle of the PWM signal.
7. The integrated circuit of claim 1 , wherein the switch comprises a transistor.
8. The integrated circuit of claim 7 , wherein the transistor comprises a PMOS (p-type metal-oxide-semiconductor field effect) transistor.
9. The integrated circuit of claim 1 , wherein the sensed power comprises maximum power scaled by a ratio.
10. The integrated circuit of claim 9 , wherein the ratio comprises source voltage divided by maximum source voltage.
11. The integrated circuit of claim 9 , wherein the ratio comprises the duty cycle of the PWM signal.
12. The integrated circuit of claim 1 , wherein the source voltage is provided by a single voltage supply.
13. The integrated circuit of claim 1 , wherein the sensed power comprises sensed power values summed from a plurality of voltage supplies.
14. The integrated circuit of claim 1 , wherein the sensed power is represented by a voltage.
15. The integrated circuit of claim 1 , wherein the sensed power is represented by a current.
16. The integrated circuit of claim 1 , further comprising circuitry for limiting power.
17. A method, comprising:
configuring circuitry of an integrated circuit to convert a source voltage into a pulse-width modulation (PWM) signal, wherein the PWM signal represents the source voltage as a fraction or percentage of a maximum source voltage of a power supply of an associated system and wherein the fraction or percentage comprises an amount of time to ramp from zero to the source voltage divided by an amount of time to ramp from zero to the maximum source voltage; and
controlling a switch of the integrated circuit using the PWM signal, wherein a current sense signal is applied to a resistor for an amount of time the switch is turned on based on a duty cycle of the PWM signal to determine a sensed power of the associated system, wherein the current sense signal is proportional to a load current drawn by the system by a factor set by a transistor ratio of transistors of the integrated circuit, wherein the sensed power is the same fraction or percentage of a maximum power of the power supply of the associated system, and wherein the integrated circuit does not have a voltage constraint due to silicon process technology but rather senses source voltage and current higher than a process technology of the integrated circuit.
18. The method of claim 17 , wherein the switch comprises a transistor.
19. The method of claim 18 , wherein the transistor comprises a PMOS (p-type metal-oxide-semiconductor field effect) transistor.
20. The method of claim 17 , wherein the source voltage modulates a pulse width of the PWM signal.
21. The method of claim 17 , wherein a pulse width of the PWM signal depends on a magnitude of the source voltage.
22. The method of claim 17 , wherein the duty cycle of the PWM signal is proportional to the source voltage.
23. The method of claim 17 , wherein the duty cycle of the PWM signal is 100% when the source voltage comprises the maximum source voltage.
24. The method of claim 17 , wherein the source voltage comprises the maximum source voltage scaled by a ratio comprising the duty cycle of the PWM signal.
25. The method of claim 17 , wherein the sensed power comprises maximum power scaled by a ratio.
26. The method of claim 25 , wherein the ratio comprises source voltage divided by maximum source voltage.
27. The method of claim 25 , wherein the ratio comprises the duty cycle of the PWM signal.
28. The method of claim 17 , wherein the source voltage is provided by a single voltage supply.
29. The method of claim 17 , wherein the sensed power comprises sensed power values summed from a plurality of voltage supplies.
30. The method of claim 17 , wherein the sensed power is represented by a voltage.
31. The method of claim 17 , wherein the sensed power is represented by a current.
32. The method of claim 17 , further comprising configuring circuitry for limiting power.
33. A computer program product embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
configuring circuitry of an integrated circuit to convert a source voltage into a pulse-width modulation (PWM) signal, wherein the PWM signal represents the source voltage as a fraction or percentage of a maximum source voltage of a power supply of an associated system and wherein the fraction or percentage comprises an amount of time to ramp from zero to the source voltage divided by an amount of time to ramp from zero to the maximum source voltage; and
controlling a switch of the integrated circuit using the PWM signal, wherein a current sense signal is applied to a resistor for an amount of time the switch is turned on based on a duty cycle of the PWM signal to determine a sensed power of the associated system, wherein the current sense signal is proportional to a load current drawn by the system by a factor set by a transistor ratio of transistors of the integrated circuit, wherein the sensed power is the same fraction or percentage of a maximum power of the power supply of the associated system, and wherein the integrated circuit does not have a voltage constraint due to silicon process technology but rather senses source voltage and current higher than a process technology of the integrated circuit.
34. The computer program product of claim 33 , wherein the source voltage modulates a pulse width of the PWM signal.
35. The computer program product of claim 33 , wherein a pulse width of the PWM signal depends on a magnitude of the source voltage.
36. The computer program product of claim 33 , wherein the duty cycle of the PWM signal is proportional to the source voltage.
37. The computer program product of claim 33 , wherein the duty cycle of the PWM signal is 100% when the source voltage comprises the maximum source voltage.
38. The computer program product of claim 33 , wherein the source voltage comprises the maximum source voltage scaled by a ratio comprising the duty cycle of the PWM signal.
39. The computer program product of claim 33 , wherein the switch comprises a transistor.
40. The computer program product of claim 39 , wherein the transistor comprises a PMOS (p-type metal-oxide-semiconductor field effect) transistor.
41. The computer program product of claim 33 , wherein the sensed power comprises maximum power scaled by a ratio.
42. The computer program product of claim 41 , wherein the ratio comprises source voltage divided by maximum source voltage.
43. The computer program product of claim 41 , wherein the ratio comprises the duty cycle of the PWM signal.
44. The computer program product of claim 33 , wherein the source voltage is provided by a single voltage supply.
45. The computer program product of claim 33 , wherein the sensed power comprises sensed power values summed from a plurality of voltage supplies.
46. The computer program product of claim 33 , wherein the sensed power is represented by a voltage.
47. The computer program product of claim 33 , wherein the sensed power is represented by a current.
48. The computer program product of claim 33 , further comprising computer instructions for configuring circuitry for limiting power.