Highly linear analog-to-digital converter and method for nonvolatile memory
View Patent ↗A non-volatile memory has an ADC that digitizes an analog voltage in a range delimited by V 1 and V 2 into N intervals, resulting in a digital Vx with x between 1 to N. A ramp voltage Vramp(x) calibrated to rise linearly from V 1 to V 2 in x=1 to N clock cycles is used to scan the analog voltage. Vx is then given by Vx=Vramp(x). The ramp voltage is provided by a constant current charging a capacitor and has a slope proportional to a DAC resistor, R(x) that is programmable from 1 to N. In a calibration mode, the R(x) is set to N, which results in K clock cycles spanning V 1 to V 2 . In a subsequent normal mode, the DAC resistor is reset to R(K) to result in a calibrated ramp voltage that would rise from V 1 to V 2 in N clock cycles.
1. A nonvolatile memory comprising:
an analog-to-digital converter (ADC) for digitizing an analog voltage into one of N equal digital intervals delimited between first and second predetermined voltage values (V 1 ) and (V 2 ) respectively, the ADC comprising;
a clock having a series of equal clock cycles;
a ramp voltage generator for generating a ramp voltage level that rises linearly from V 1 to V 2 in N clock cycles, such that the ramp voltage level at an xth clock cycle is a digital level of the ramp voltage at a corresponding xth digital interval of N equal digital intervals between V 1 and V 2 ;
a comparator for comparing the ramp voltage level with that of a level of the analog voltage; and
a counter for counting a number of clock cycles (x′) when the ramp voltage level has risen from V 1 to match the level of the analog voltage;
wherein a digital value of the level of the analog voltage is produced as a corresponding x′th digital interval of the N equal digital intervals between V 1 and V 2 .
2. The nonvolatile memory as in claim 1 , wherein said ramp voltage generator comprises:
a capacitor;
a programmable constant current source; and
a linear ramp voltage produced by said programmable constant current source charging said capacitor.
3. The nonvolatile memory as in claim 2 , wherein:
said ramp voltage generator further comprises a programmable digital-to-analog converter (DAC) resistor; and
the programmable constant current source is proportional to a resistance of said programmable DAC resistor.
4. The nonvolatile memory as in claim 3 , wherein:
said ramp voltage generator has a ramp rate proportional to the programmable DAC resistor of resistance R(x) within a range between R( 1 ) to R(N).
5. The nonvolatile memory as in claim 4 , further comprising:
a control module for controlling operations of said ramp voltage generator and said counter, the operations including:
setting the programmable DAC resistor to R(N) for the ramp voltage generator to generate an uncalibrated ramp voltage;
counting a number of clock cycles (K) for the uncalibrated ramp voltage to rise from V 1 to V 2 ; and
resetting the programmable DAC resistor in proportion to K for the ramp voltage generator to generate a calibrated ramp voltage with a voltage level that rises from V 1 to V 2 in said N clock cycles.
6. The nonvolatile memory as in claim 1 , wherein:
said ADC is part of the nonvolatile memory for digitizing a temperature dependent voltage from a temperature sensor into a digital temperature code; and
the digital temperature code is used by a voltage generator of the nonvolatile memory to compensate for temperature.
7. The nonvolatile memory as in claim 1 , wherein:
the non-volatile memory includes a plurality of memory cells; and
said ADC is for digitizing a voltage associated with sensing of the plurality of memory cells.
8. The nonvolatile memory as in claim 7 , wherein:
said plurality of memory cells are organized in a two-dimensional array.
9. The nonvolatile memory as in claim 7 , wherein:
said plurality of memory cells are organized in a three-dimensional array.
10. The nonvolatile memory as in claim 7 , wherein:
said plurality of memory cells are arranged in a NAND type architecture.
11. A nonvolatile memory comprising:
a clock having a series of equal clock cycles;
a ramp voltage generator for generating a ramp voltage level that rises linearly from a first predetermined voltage value (V 1 ) to a second predetermined voltage value (V 2 ) in N clock cycles, such that the ramp voltage level at an xth clock cycle is a digital level of the ramp voltage at a corresponding xth digital interval of N equal digital intervals between V 1 and V 2 ;
a comparator for comparing the ramp voltage level with that of a level of an analog voltage; and
a counter for counting a number of clock cycles (x′) when the ramp voltage level has risen from V 1 to match the level of the analog voltage;
wherein a digital value of the level of the analog voltage is produced as a corresponding x′th digital interval of the N equal digital intervals between V 1 and V 2 .
12. A method of operating a nonvolatile memory, comprising:
providing an analog voltage to be digitized into one of N equal digital intervals delimited between first and second predetermined voltage values (V 1 ) and (V 2 ) respectively;
providing a clock having a series of equal clock cycles;
providing a ramp voltage having a ramp voltage level that rises linearly from V 1 to V 2 in N clock cycles, such that the ramp voltage level at an xth clock cycle is a digital level of the ramp voltage at a corresponding xth digital interval of the N equal digital intervals between V 1 and V 2 ;
comparing the ramp voltage level with that of a level of the analog voltage;
counting a number of clock cycles (x′) when the ramp voltage level has risen from V 1 to match the level of the analog voltage; and
digitizing the level of the analog voltage to be at the corresponding x′th digital interval of the N equal digital intervals between V 1 and V 2 .
13. The method as in claim 12 , wherein said providing the ramp voltage further comprises:
charging a capacitor by a programmable constant current to provide the ramp voltage.
14. The method as in claim 13 , further comprising:
providing a programmable digital-to-analog converter (DAC) resistor; and
setting a resistance of the programmable DAC resistor proportionally to program the programmable constant current.
15. The method as in claim 14 , wherein said ramp voltage has a ramp rate proportional to the programmable DAC resistor of resistance R(x) within a range between R( 1 ) to R(N).
16. The method as in claim 15 , further comprising:
setting the programmable DAC resistor to R(N) to generate an uncalibrated ramp voltage;
counting a number of clock cycles (K) for the uncalibrated ramp voltage to rise from V 1 to V 2 ; and
resetting the programmable DAC resistor in proportion to K to generate a calibrated ramp voltage with a voltage level that rises from V 1 to V 2 in said N clock cycles.
17. The method as in claim 12 , wherein:
said analog voltage is a temperature dependent voltage from a temperature sensor in the nonvolatile memory; and
wherein the digitized level of the analog voltage is used by a voltage generator of the nonvolatile memory to compensate for temperature.