Method and apparatus for calibrating comparator offset of successive-approximation-register analog-to-digital converter
A circuit and method compensates for comparator offset in a successive approximation register analog-to-digital converter. The circuit includes a multiplexed sampler to sample either a common mode voltage or an input signal. The sampled signal is added to a conversion voltage and an offset correction voltage and input to a comparator. The comparator determines a polarity of deviation of the sum of the sampled signal, conversion voltage and off-set correction voltage. Based on the polarity, the offset correction voltage and the conversion voltage are alternately subjected to a successive approximation process to compensate for the offset of the sum from the sampled input signal or sampled common voltage signal.
1. A circuit comprising:
a multiplexed sampling network sampling either an input voltage or a common-mode voltage into a sampled voltage in accordance with a sampling signal and a status of a foreground calibration indicator;
a first digital-to-analog converter outputting a conversion voltage in response to a conversion code;
a second digital-to-analog converter outputting an offset-correction voltage in response to an offset-correction code;
a summing circuit receiving the sampled voltage, the conversion voltage, and the offset-correction voltage and outputting an error voltage;
a comparator receiving the error voltage and outputting a binary decision; and
a successive-approximation-register finite state machine receiving the binary decision and outputting an output data, the sampling signal, the foreground calibration indicator, the conversion code, and the offset-correction code,
wherein the finite stage machine includes a foreground calibration state and a normal operation state;
wherein when the finite state machine operates in the foreground calibration state, the common-mode voltage is sampled, the conversion code is set to a common-mode code, and a calibrated value of the offset-correction code is established by successive approximation and
wherein when the finite state machine is in the normal operation state, the input voltage is sampled, the offset-correction code is set to the calibrated value, and the conversion code is established by successive approximation.
2. The circuit of claim 1 , wherein the common-mode voltage is equal to a statistical mean of the input voltage.
3. The circuit of claim 1 , wherein a value of the conversion voltage in response to the common-mode code is approximately equal to the common-mode voltage.
4. The circuit of claim 3 , wherein a value of the offset-correction voltage in response to the calibrated value of the offset-correction code is approximately equal to an offset voltage of the comparator.
5. The circuit of claim 1 , wherein the output data comprises a final value of the conversion code at the end of the successive approximation in the normal operation mode.
6. The circuit of claim 5 , wherein the calibrated value of the offset-correction code is adapted based on a statistical mean of the output data in the normal operation mode.
7. The circuit of claim 1 , wherein the first digital-to-analog converter comprises a plurality of capacitors, each of said capacitors comprising a first end and a second end, the first end being coupled to a common node, and the second end being coupled to one of a first reference voltage and a second reference voltage in accordance with a respective bit of the conversion code.
8. The circuit of claim 1 , wherein the second digital-to-analog converter comprises a plurality of capacitors, each of said capacitors comprising a first end and a second end, the first end being coupled to a common node, and the second end being coupled to one of a first reference voltage and a second reference voltage in accordance with a respective bit of the offset-correction code.
9. The circuit of claim 1 , wherein a resolution of the second digital-to-analog converter is higher than a resolution of the first digital-to-analog converter.
10. A method comprising:
using a first digital-to-analog converter to generate a conversion voltage in response to a conversion code;
using a second digital-to-analog converter to generate an offset-correction voltage in response to an offset-correction code;
using a summing circuit to generate an error voltage representing a sum of a sampled voltage, the conversion voltage, and the offset-correction voltage;
using a comparator to generate a binary decision indicating a polarity of the error voltage;
performing a first successive approximation including:
setting the conversion code to a common-mode code;
setting the offset-correction code to a neutral code;
sampling a common-mode voltage into the sampled voltage;
iteratively adapting the offset-correction code in accordance with the binary decision using successive approximation; and
saving a final value of the offset-correction code as a calibrated value;
performing a second successive approximation including:
setting the offset-correction code to the neutral code;
setting the conversion code to the common-mode code;
sampling an input voltage into the sampled voltage;
setting the offset-correction code to the calibrated value; and
iteratively adapting the conversion code in accordance with the binary decision using successive approximation; and
outputting an output data using a final value of the conversion code.
11. The method of claim 10 , wherein iteratively adapting the offset-correction code in accordance with the binary decision using successive approximation comprises: conducting a plurality of iterations, each of said iterations increases a value of the offset-correction code when the binary decision is one, or otherwise decreases the value of the offset-correction code.
12. The method of claim 10 , wherein iteratively adapting the conversion code in accordance with the binary decision using successive approximation comprises: conducting a plurality of iterations, each of said iterations increases a value of the conversion code when the binary decision is one or otherwise decreases the value of the conversion code.
13. The method of claim 10 , wherein a value of the conversion voltage in response to the common-mode code is approximately equal to the common-mode voltage.
14. The method of claim 10 , wherein a value of the offset-correction voltage in response to the calibrated value of the offset-correction code is approximately equal to an offset voltage of the comparator.
15. The method of claim 10 , wherein the first digital-to-analog converter comprises a plurality of capacitors, each of said capacitors comprising a first end and a second end, said method including coupling the first end to a common node and coupling the second end to either a first reference voltage or a second reference voltage in accordance with a respective bit of the conversion code.
16. The method of claim 10 , wherein the second digital-to-analog converter comprises a plurality of capacitors, each of said capacitors comprising a first end and a second end, said method including the first end coupling to a common node and coupling the second end to either a first reference voltage or a second reference voltage in accordance with a respective bit of the offset-correction code.
17. The method of claim 10 , wherein a resolution of the second digital-to-analog converter is higher than a resolution of the first digital-to-analog converter.
18. The method of claim 10 further comprising: adapting the calibrated value of the offset-correction code based on a statistical mean of the output data.