Semiconductor device

1. A semiconductor device comprising:

a plurality of memory cells;

an access circuit configured to perform a data read operation, a data write operation, and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform; and

a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation,

wherein the first mode comprises an idle mode and the second mode comprises a deep power down mode.

2. The semiconductor device as claimed in claim 1 , wherein the access circuit is configured to further respond to second command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to maintain the second mode.

3. The semiconductor device as claimed in claim 2 , further comprising a plurality of terminals, the first command information being different in combination of logic levels at the terminals from the second command information.

4. The semiconductor device as claimed in claim 3 , wherein the terminals comprises a chip select terminal and a clock enable terminal.

5. The semiconductor device as claimed in claim 1 ,

wherein the data refresh operation comprises a data self-refresh operation.

6. The semiconductor device as claimed in claim 1 ,

wherein the plurality of memory cells are coupled to one another in a same rank.

7. A system, comprising:

a memory controller configured to issue a plurality of commands that include a read command, a write command, and a refresh command, the refresh command including first command information or second command information; and

a plurality of memory devices configured to receive the plurality of commands in common from the memory controller, each of the plurality of memory devices comprising:

a plurality of memory cells,

an access circuit configured to perform a data read operation, a data write operation, and a data refresh operation on the memory cells in response to the plurality of commands from the memory controller, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to the first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation,

wherein the first mode comprises an idle mode and the second mode comprises a deep power down mode.

8. The system as claimed in claim 7 , wherein the access circuit is configured to further respond to the second command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to maintain the second mode.

9. The system as claimed in claim 8 , each memory device of the plurality of memory devices further comprising a plurality of terminals, the first command information being different in combination of logic levels at the terminals from the second command information.

10. The system as claimed in claim 9 , wherein each terminal of the plurality of terminals comprises a chip select terminal and a clock enable terminal.

11. The system as claimed in claim 7 ,

wherein the data refresh operation comprises a data self-refresh operation.

12. A method comprising:

bringing a first memory device into a first mode in which the first memory device is ready to operate, and bringing a second memory device into a second mode in which the second memory device is not ready to operate, the first memory device comprising at least one first memory cell, and the second memory device comprising at least one second memory cell; and

supplying first command information in common to the first and second memory devices to cause the first memory device to perform a data refresh operation on the at least one first memory cell, and to cause the second memory device to exit from the second mode and then to perform a data refresh operation on the at least one second memory cell.

13. The method as claimed in claim 12 , further comprising:

supplying second command information in common to the first and second memory devices to cause the first memory device to perform the data refresh operation on the at least one first memory cell, and to cause the second memory device to maintain the second mode.

14. The method as claimed in claim 13 , wherein the first command information is different in combination of logic levels from the second command information.

15. The method as claimed in claim 14 , wherein the first command information and the second command information are respectively represented by a chip select signal and a clock enable signal.

16. The method as claimed in claim 15 ,

wherein the first mode comprises an idle mode and the second mode comprises a deep power down mode.

17. The method as claimed in claim 16 ,

wherein the data refresh operation comprises a data self-refresh operation.

18. The method as claimed in claim 17 ,

wherein the first memory device and the second memory device are operated by a same chip select signal and a per DRAM addressability.