Memory fault patching using pre-existing memory structures
A computer architecture addresses intermittent memory faults by exploiting redundancy inherent in a hierarchical memory structure, for example, as data moves through various cache levels and registers before use by the processor. Accesses to data from faulted memory areas is diverted to a secondary memory structure holding that data and the secondary memory structure is flagged to increase the persistence of the stored data used for patching against normal updating policies.
1. An electronic computer comprising:
a processing unit for executing instructions operating on data;
an electronic memory system adapted to hold instruction values and data values and communicate them with the processing unit, the electronic memory system providing a hierarchy of memory storage structures providing redundant storage of the instruction values and data values among the memory storage structures;
memory updating circuitry operating to update the values stored in the hierarchy of memory storage structures between different memory storage structure per the hierarchy; and
data access circuitry tracking intermittent faults in first memory locations in a first memory storage structure and, at times when there is an intermittent fault in the first memory location, operating to:
(a) direct memory accesses intended for the first memory locations to corresponding second memory locations of a second data structure providing redundant storage of data with the first memory locations to patch the first memory locations; and
(b) increase a persistence of data in second memory locations against updating by the memory updating circuitry in comparison to the persistence of the data in the second memory locations when there is no intermittent fault in the first memory locations.
2. The electronic computer of claim 1 wherein the first and second data structures each provide additional functions unrelated to patching the first memory locations.
3. The electronic computer of claim 2 wherein the first memory structure is an instruction value cache and the second memory structure is selected from the group consisting of a micro-op cache and a miss-status handling register for instruction values.
4. The electronic computer of claim 3 wherein the second memory location includes memory locations from both the micro-op cache and the miss-status handling registers for instruction values.
5. The electronic computer of claim 2 wherein the first memory structure is a data value cache and the second memory structure is selected from the group consisting of a store queue and miss-status handling registers for data values.
6. The electronic computer of claim 5 wherein the second memory location includes memory locations from both the store queue and the miss-status handling registers for data values.
7. The electronic computer of claim 2 wherein the first memory location is a first cache memory and the second memory location is a second cache memory at a different cache level than the first cache memory.
8. The electronic computer of claim 2 wherein the first memory location is a DRAM random access memory and the second memory location is a SRAM cache memory.
9. The electronic computer of claim 1 wherein the data access circuitry directs memory accesses intended for the first memory locations to corresponding second memory locations of a second data structure as a function of whether there is an intermittent fault in the first memory location.
10. The electronic computer of claim 1 wherein the data access circuitry includes a fault record identifying intermittent faults in the first memory storage structure and wherein the data of the fault record changes as a function of at least one input value selected from the group consisting of a value indicating an operating voltage of the first data structure, a value indicating an operating temperature of the first memory structure, and a value indicating a result of a periodic memory check of the first memory structure.
11. The electronic computer of claim 10 wherein the fault record is a lookup table of predetermined values relating faults to different operating voltages of the first data structure.
12. The electronic computer of claim 1 wherein the data access circuitry further includes a policy circuit overriding the increase in persistence of the data according to an assessment of operation of the second memory structure for a purpose unrelated to patching the first memory structure.
13. The electronic computer of claim 1 wherein the data access circuitry further includes a policy circuit overriding the increase in persistence of the data as a function of at least one of the group consisting of; usefulness of data in the second memory locations for patching indicated by frequency of access, percentage of the second data structure having increased persistence for patching, a measure of access misses in the second data structure; and a determination of whether the processor will stall if allocation of new entries is delayed.
14. The electronic computer of claim 1 wherein the hierarchy of memory locations provides for memory structures providing a range of different tradeoffs between data access speeds and data storage costs.
15. The electronic computer of claim 1 wherein the hierarchy of memory structures includes at least three of a micro-op cache, an instruction cache, a data cache, miss-status handling registers, an L1 cache, an L2 cache, an L3 cache, and a dynamic random access memory array.
16. The electronic computer of claim 1 wherein the second memory structure provides an architecture more resistant to errors than the first memory structure.
17. The electronic computer of claim 1 wherein the data access circuitry sets persistence bits in the second memory structure that are read by the memory updating circuitry to avoid updating a portion of the second memory with set persistence bits.