Processor register error correction management

1. A method of processor register protection management, the method comprising:

determining a sensitive logical register for executable code generated by a compiler;

generating an error-correction table identifying the sensitive logical register; and

storing the error-correction table in a memory accessible by a processor, wherein the processor is configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

2. The method of claim 1 , further comprising:

receiving a register write instruction for a logical register;

determining whether the logical register is identified by the error-correction table in response to receiving the register write instruction; and

writing a data duplicate of the logical register in a memory location in response to determining that the logical register is in the error-correction table.

3. The method of claim 1 , further comprising:

receiving a read instruction for a logical register;

determining whether an error exists in the logical register

determining whether a data duplicate of the logical register exists, in response to determining than an error exists in the register; and

overwriting the logical register with the data duplicate.

4. The method of claim 1 , wherein the sensitive logical register for executable code generated by the compiler is determined using an error injection analysis.

5. The method of claim 1 , wherein the sensitive logical register for executable code generated by the compiler is determined using static analysis.

6. The method of claim 1 , wherein the memory is located within the processor.

7. The method of claim 1 , wherein the memory is located external to the processor.

8. The method of claim 1 , further comprising:

determining that a renamed register is generated from a logical register;

determining whether the logical register is identified by the error-correction table

modifying the error-correction table to identify the renamed register in response to determining that the logical register is identified by the error-correction table.

9. A system for processor register protection management, the system comprising:

a memory storing an error-correction table identifying a sensitive logical register for executable code generated by a compiler; and

a processor having a plurality of registers, the processor configured to access the error-correction table in the memory and generate a duplicate register for the sensitive logical register identified by the error-correction table.

10. The system of claim 9 , wherein the processor is further configured to:

receive a register write instruction for a logical register;

determine whether the logical register is identified by the error-correction table in response to receiving the register write instruction; and

write a data duplicate of the logical register in a physical register in response to determining that the logical register is in the error-correction table.

11. The system of claim 9 , wherein the processor is further configured to:

receive a read instruction for a logical register;

determine whether an error exists in the logical register

determine whether a data duplicate of the logical register exists, in response to determining than an error exists in the register; and

overwrite the logical register with the data duplicate.

12. The system of claim 9 , wherein the sensitive logical register for executable code generated by the compiler is determined using an error injection analysis.

13. The system of claim 9 , wherein the sensitive logical register for executable code generated by the compiler is determined using static analysis.

14. The system of claim 9 , wherein the memory is located within the processor.

15. The system of claim 9 , wherein the memory is located external to the processor.

16. The system of claim 9 , wherein the processor is further configured to:

determine that a renamed register is generated from a logical register;

determine whether the logical register is identified by the error-correction table; and

modify the error-correction table to identify the renamed register in response to determining that the logical register is identified by the error-correction table.

17. A method of processor register protection management, the method comprising:

determining a floating point logical register for executable code generated by a compiler, the floating point logical register configured to store a floating point including a signage bit, a plurality of exponent bits, and a plurality of fraction bits, the plurality of fraction bits including a higher order bit and a lower order bit;

generating a plurality of parity bits for the floating point logical register, the plurality of parity bits corresponding to the signage bit, the plurality of exponent bits, and the higher order bit.

18. The method of claim 17 , further comprising:

determining a sensitive logical register for executable code generated by a compiler;

generating an error-correction table identifying the sensitive logical register; and

storing the error-correction table in a memory accessible by a processor, wherein the processor is configured to generate a duplicate register the sensitive logical register identified by the error-correction table.

19. The method of claim 18 , further comprising:

receiving a register write instruction for a logical register;

determining whether the logical register is identified by the error-correction table in response to receiving the register write instruction; and

writing a data duplicate of the logical register in a physical register in response to determining that the logical register is in the error-correction table.

20. The method of claim 18 , further comprising:

receiving a read instruction for a logical register;

determining whether an error exists in the logical register

determining whether a data duplicate of the logical register exists, in response to determining than an error exists in the register; and

overwriting the logical register with the data duplicate.

21. A computer program product for processor register protection management, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method comprising:

determining a sensitive logical register for executable code generated by a compiler;

generating an error-correction table identifying the sensitive logical register; and

storing the error-correction table in a memory accessible by a processor, wherein the processor is configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

22. The computer program product of claim 21 , wherein the program instructions cause the computer to perform the method, the method further comprising:

receiving a register write instruction for a logical register;

determining whether the logical register is identified by the error-correction table in response to receiving the register write instruction; and

writing a data duplicate of the logical register in a physical register in response to determining that the logical register is in the error-correction table.

23. The computer program product of claim 21 , wherein the program instructions cause the computer to perform the method, the method further comprising:

receiving a read instruction for a logical register;

determining whether an error exists in the logical register

determining whether a data duplicate of the logical register exists, in response to determining than an error exists in the register; and

overwriting the logical register with the data duplicate;

determining a floating point logical register for executable code generated by a compiler, the floating point logical register configured to store a floating point including a signage bit, a plurality of exponent bits, and a plurality of fraction bits, the plurality of fraction bits including a higher order bit and a lower order bit;

generating a plurality of parity bits for the floating point logical register, the plurality of parity bits corresponding to the signage bit, the plurality of exponent bits, and the higher order bit.