METHODS AND APPARATUSES FOR ULTRA-LOW-POWER SYSTEM ON A CHIP (SoC) ACTIVITY WEARABLE DEVICES
An always-on chip incorporated inside an activity wearable device implemented as a System-On-a-Chip (SoC). The device includes a MCU and DSP and audio CODEC and a BLE circuit to detect user activation commands. The user wakeup command is used to wake up the main application processor on the system. Ultra low power consumption may be realized by implementing the CMOS die using sub-threshold technology and by using power and battery management algorithms based on the human activity detected by the integrated sensors.
1 . A method to implement an always-on chip incorporated into a wearable device or Smart Phone or Smart Watch or IoT devices implemented as a system on a chip comprising one or more of the following blocks:
An audio ADC+DAC for audio output and input;
An audio Compressor+Decompressor for playback and recording of compressed audio;
A wireless data transmission functionality for data transmission and or low-power protocol processing; and
An integrated microcontroller unit and or integrated DSP unit to implement a data analysis mechanism, a data communication mechanism, audio input and output and wakeup gesture detection;
Finally included also a Power Management Unit (PMU), a Clock Management Unit (CMU) and a Battery Management Unit (BMU).
2 . The device of claim 1 wherein the ASIC includes one or more logic cells or memory cells or analog blocks capable of operating at a sub-threshold operating voltage (for example 0.45 v or 0.55 v) to reduce the power consumption to an ultra-low target.
3 . The device of claim 1 wherein the Power Management Unit uses knowledge of the lowest required frequency to process the required audio, sensors, gestures and wireless communication to activate a required logic at a rate based on the speed of the user activity.
4 . The device of claim 1 wherein different mechanism at the device and or external host processor can be woken-up upon detection of required user activity.
5 . The device of claim 1 wherein the Power Management Unit (PMU) comprises a scheduler mechanism that operates a portion of the device during each of multiple scheduling intervals in order to reduce spikes from the battery and a programmable DC 2 DC convertor which can change his output voltage dynamically from the Sub-Threshold voltage domain to the standard voltage (for example from 0.45 v to 1.1 v) by SW control depends on the required processing speed.
6 . The device of claim 1 wherein the Clock Management Unit (CMU) can control frequency of each component separately per required usage operation.