IP Library Granted Patent US 11,004,698
Granted Patent B2
US 11,004,698 · App. 14/513,456 · Granted May 11, 2021

Power module package

Inventors: Keunhyuk Lee (Jiangsu, CN); Oseob Jeon (Seoul, KR); Joon-seo Son (Seoul, KR); Seungwon Im (Gyeonggi-do, KR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/565H01L23/3121H01L23/3735H01L23/49811H01L23/49844H01L25/072H05K3/284H01L24/32H01L24/40H01L24/48H01L24/73H01L2021/60015H01L2021/60277H01L2224/2929H01L2224/29101H01L2224/29301H01L2224/32225H01L2224/40095H01L2224/40225H01L2224/48091H01L2224/48227H01L2224/73221H01L2224/73263H01L2224/73265H01L2224/8385H01L2224/83801H01L2224/84815H01L2224/92246H01L2224/92247H01L2924/00014H01L2924/07811H01L2924/13055H01L2924/13091H01L2924/181H05K3/4015H05K2201/10318H05K2201/10333H05K2203/1316Y10T29/49133
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Quick Facts
Patent No.
US 11,004,698
App. No.
14/513,456
Granted
May 11, 2021
Kind
B2
Abstract

Provided is a power module package including: a substrate; at least one electrode arranged on the substrate; and an encapsulation member covering at least a portion of the substrate, the encapsulation member including a housing unit housing the at least one electrode. The at least one electrode is spaced apart from the encapsulation member.

Claims (42)

1. A power module package, comprising:

a substrate;

at least one electrode mounted on the substrate; and

an encapsulation member, coupled to and covering at least a portion of the substrate, the encapsulation member including a housing unit housing the at least one electrode,

the at least one electrode having a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the at least one electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate having a portion exposed within the open space, the encapsulation member having an open cross-section perpendicular to an upper surface of the substrate and aligned along an extension line intersecting the at least one electrode.

2. The power module package of claim 1 , wherein the housing unit houses two or more electrodes including the at least one electrode.

3. The power module package of claim 1 , wherein the at least one electrode has an exposed upper surface and an exposed portion of the conductive sidewall extending above the uppermost surface of the encapsulation member.

4. The power module package of claim 1 , wherein the at least one electrode has a pillar shape with a uniform width.

5. The power module package of claim 4 , wherein the at least one electrode has a cross-sectional area in a direction perpendicular to an upper surface of the substrate, and the cross-sectional area is constant or varies along the direction.

6. The power module package of claim 1 , wherein the substrate comprises:

an insulation body;

an upper conductive pattern formed on an upper surface of the insulation body; and a lower conductive pattern formed on a lower surface of the insulation body,

the at least one electrode being disposed on a portion of the upper conductive pattern.

7. The power module package of claim 6 , wherein the housing unit exposes a portion of the upper conductive pattern or a portion of the insulation body.

8. The power module package of claim 1 , further comprising:

at least one semiconductor chip arranged on the substrate; and

a wiring member electrically connecting the at least one semiconductor chip and the at least one electrode,

the at least one semiconductor chip and the wiring member being covered by the encapsulation member.

9. The power module package of claim 1 , wherein the conductive sidewall of the at least one electrode is aligned along a direction non-parallel to the substrate.

10. The power module package of claim 1 , further comprising:

a bonding member disposed between a bottom end of the at least one electrode and the substrate, the bonding member being spaced apart from, and not in contact with the encapsulation member.

11. The power module package of claim 1 , wherein the encapsulation member is formed after the at least one electrode is coupled to the substrate via a bonding member.

12. A power module package, comprising:

a substrate;

a first electrode and a second electrode arranged on the substrate; and

an encapsulation member having a first portion encapsulating a portion of the substrate and surrounding at least a portion of the first electrode, the encapsulation member being separated from the first electrode by a first distance,

the first electrode and the second electrode each having a conductive sidewall exposed to the encapsulation member,

the first electrode having an upper surface and a portion of the conductive sidewall extending above the encapsulation member,

the conductive sidewall of the first electrode not being in contact with the first portion of the encapsulation member, such that there is open space of a first distance between the conductive sidewall of the first electrode and the first portion of the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member,

the conductive sidewall of the second electrode not being in contact with the first portion of the encapsulation member, such that there is open space of a second distance between the conductive sidewall of the second electrode and the first portion of the encapsulation member from the uppermost surface to the bottommost surface of the encapsulation member, the second distance being different from the first distance.

13. The power module package of claim 12 , wherein the upper surface of the second electrode is disposed higher than the uppermost surface of the encapsulation member relative to an upper surface of the substrate.

14. The power module package of claim 12 , wherein the encapsulation member has a closed cross-section aligned along a direction perpendicular to an upper surface of the substrate.

15. The power module package of claim 12 , wherein the first electrode has a width greater than a width of the second electrode.

16. An apparatus, comprising:

a substrate;

a first electrode and a second electrode directly mounted on the substrate, the first electrode and the second electrode each being aligned along a direction non-parallel to the substrate; and

an encapsulation member disposed on at least a portion of the substrate, the encapsulation member having an opening surrounding the first electrode and the second electrode,

the first electrode and the second electrode each having a conductive sidewall exposed to a sidewall of the opening of the encapsulation member, the conductive sidewall of each of the first electrode and the second electrode not being in contact with the sidewall of the encapsulation member, such that, from an uppermost surface to a bottommost surface of the encapsulation member:

there is open space between the first electrode and the sidewall of the encapsulation member, the substrate having a first portion exposed within the open space between the first electrode and the sidewall of the encapsulation member, and

there is open space between the second electrode and the sidewall of the encapsulation member, the substrate having a second portion exposed within the open space between the second electrode and the sidewall of the encapsulation member.

17. The apparatus of claim 16 , wherein the first electrode has an exposed upper surface and an exposed portion of the conductive sidewall extending above the uppermost surface of the encapsulation member.

18. The apparatus of claim 16 , wherein the first electrode has a cross-sectional area less than a cross-sectional area of the opening.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: LEE, KEUNHYUK; JEON, OSEOB; SON, JOON-SEO; IM, SEUNGWON
To: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
Reel/Frame 034133/0721 →