Biasing of unselected blocks of non-volatile memory to reduce loading
View Patent ↗Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND memory of the BiCS type. When multiple blocks are commonly decoded, a decoded group may include both selected and unselected blocks. The word lines of a selected block are biased according the operation, while the word lines of the non-selected blocks of the group are set at the level of the source line. This reduces the amount of loading on the source line due to less capacitance between the source line and word lines.
1. A memory circuit comprising:
an array of non-volatile memory cells having a plurality of blocks, each formed of a plurality of NAND strings having multiple memory cells connected in series and connected along word lines, where each of a block's NAND strings are connected to a common source line among a plurality of common source lines through a local source line interconnect;
decoding circuitry connected to the array to select blocks for a memory operation, where the decoding circuitry selects blocks in multi-block groups, the blocks of a group sharing the same common source line among the plurality of common source lines; and
driver circuitry connected to the array, wherein, when performing the memory operation, the driver circuitry applies a source line voltage greater than zero to the shared common source line of a selected group, applies operating voltages to the word lines of a selected block within the selected group, and applies the source line voltage to the word lines of unselected blocks of the selected group.
2. The memory circuit of claim 1 , wherein the memory operation is a sensing operation, and the source line voltage and the operating voltages applied to the word lines of the selected block are for reading a page of data therefrom.
3. The memory circuit of claim 1 , wherein the memory operation is a programming operation, and the source line voltage and the operating voltages applied to the word lines of the selected block are for writing a page of data therefrom.
4. The memory circuit of claim 1 , wherein the memory operation is an erase operation, and the source line voltage and the operating voltages applied to the word lines of the selected block are for erasing the selected block.
5. The memory circuit of claim 1 , wherein a multi-block group has four blocks.
6. The memory circuit of claim 1 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.
7. The memory circuit of claim 6 , wherein the NAND strings and the local source line interconnects run in a vertical direction relative to the substrate, and the word lines run in a horizontal direction relative to the substrate.
8. The memory circuit of claim 6 , wherein the plurality of common source lines run in a horizontal direction relative to the substrate.
9. A monolithic three-dimensional semiconductor memory device comprising:
an array of non-volatile memory cells having a plurality of blocks, each formed of a plurality of NAND strings having multiple memory cells connected in series and connected along word lines, where each of a block's NAND strings are connected to a local source line interconnect among a plurality of source lines interconnects,
wherein the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium, the NAND strings and the local source line interconnects run in a vertical direction relative to the substrate, the word lines run in a horizontal direction relative to the substrate, and each of the local source line interconnects are connected to one of a plurality of global source lines running in the horizontal direction relative to the substrate;
decoding circuitry connected to the array to select blocks for a memory operation, where the decoding circuitry selects blocks in multi-block groups, the blocks of a group sharing the same global source line among the plurality of global source lines; and
driver circuitry connected to the array, wherein, when performing the memory operation, the driver circuitry applies a source line voltage above ground to the shared global source line of a selected group, applies operating voltages to the word lines of a selected block within the selected group, and applies the source line voltage to the word lines of unselected blocks within the selected group.
10. The monolithic three-dimensional semiconductor memory device of claim 9 , wherein the memory operation is a sensing operation, and the source line voltage and the operating voltages applied to the word lines of the selected block are for reading a page of data therefrom.
11. The monolithic three-dimensional semiconductor memory device of claim 9 , wherein the memory operation is a programming operation and the operating voltages applied to the word lines of the selected block are for writing a page of data therefrom.
12. The monolithic three-dimensional semiconductor memory device of claim 9 , wherein the memory operation is an erase operation and the operating voltages applied to the word lines of the selected block are for erasing the selected block.
13. The monolithic three-dimensional semiconductor memory device of claim 9 , wherein a multi-block group has four blocks.
14. A method, comprising:
performing a memory operation in a memory circuit, the memory circuit comprising an array of non-volatile memory cells having a plurality of blocks, each formed of a plurality of NAND strings having multiple memory cells connected in series and connected along word lines, where each of a block's NAND strings are connected to a common source line among a plurality of common source lines through a local source line interconnect, the memory operation including:
selecting by decoding circuitry connected to the array for the memory operation, where the decoding circuitry selects blocks in multi-block groups, where the blocks of a group share the same common source line among the plurality of common source lines; and
biasing by driver circuitry of a selected groups of block, including:
applying a source line voltage higher than ground to the shared common source line of the selected group;
applying operating voltages to the word lines of a selected block within the selected group; and
applying the source line voltage to the word lines of unselected blocks of the selected group.
15. The method of claim 14 wherein the memory operation is a sensing operation, and the source line voltage and the operating voltages applied to the word lines of the selected block are for reading a page of data therefrom.
16. The method of claim 14 , wherein the memory operation is a programming operation, and the source line voltage and the operating voltages applied to the word lines of the selected block are for writing a page of data therefrom.
17. The method of claim 14 , wherein the memory operation is an erase operation, and the source line voltage and the operating voltages applied to the word lines of the selected block are for erasing the selected block.
18. The method of claim 14 , wherein a multi-block group has four blocks.
19. The method of claim 14 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.
20. The method of claim 19 , wherein the NAND strings and the local source line interconnects run in a vertical direction relative to the substrate, and the word lines run in a horizontal direction relative to the substrate.
21. The method of claim 19 , wherein the plurality of common source lines run in a horizontal direction relative to the substrate.