IP Library › Granted Patent US 9,431,111
Granted Patent B2
US 9,431,111 · App. 14/515,902 · Granted Aug 30, 2016

One time programming memory cell, array structure and operating method thereof

Inventors: Meng-Yi Wu (Hsinchu County, TW); Hsin-Ming Chen (Hsinchu, TW)
Assignee: EMEMORY TECHNOLOGY INC.
G11C16/08G11C16/10G11C16/26G11C17/04G11C17/08G11C17/146G11C17/16G11C17/18G11C29/76H01L23/528H01L27/0629H01L27/11206H01L27/11524H01L29/1079H01L29/4916H01L29/93H03K3/356182H01L23/5252
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Quick Facts
Patent No.
US 9,431,111
App. No.
14/515,902
Granted
Aug 30, 2016
Kind
B2
Abstract

A one time programming memory cell includes a transistor, a first varactor, and a second varactor. The transistor has a gate terminal, a source terminal and a drain terminal. The gate terminal of the transistor is connected with a word line. The source terminal of the transistor is connected with a bit line. A first end of the first varactor is connected with the drain terminal of the transistor. A second end of the first varactor is connected with a first program line. A first end of the second varactor is connected with the drain terminal of the transistor. A second end of the second varactor is connected with a second program line.

Claims (5)

1. An operating method of an array structure, the array structure having a first one time programming memory cell comprising: a first transistor having a gate terminal connected with a first word line, a source terminal connected with a first bit line and a drain terminal, a first varactor having a first end connected with the drain terminal of the first transistor and a second end connected with a first program line, and a second varactor having a third end connected with the drain terminal of the first transistor and a fourth end connected with a second program line, the operating method comprising steps of:

performing a first program process to turn the first varactor of the first one time programming memory cell into a first resistor;

performing a verification process to read a first read current of the first one time programming memory cell; and

judging whether the first one time programming memory cell is a failed memory cell according to the first read current, wherein if the first one time programming memory cell is verified as the failed memory cell, a second program process is performed to turn the second varactor of the first one time programming memory cell into a second resistor.

2. The operating method as claimed in claim 1 , wherein if the first read current is lower than a reference current, the first one time programming memory cell is verified as the failed memory cell.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2014
From: WU, MENG-YI; CHEN, HSIN-MING
To: EMEMORY TECHNOLOGY INC.
Reel/Frame 033963/0112 →
Continuity (2)
Provisional Application 62022166 · Jul 8, 2014
Related Publication 20160013193A1 · Jan 14, 2016