Power amplifier having separate interconnects for DC bias and RF matching networks

1. An amplifier cell apparatus, comprising:

an RF input node;

a first power transistor in communication with the input node through a first input impedance matching network;

a second power transistor in communication with the input node through a second input impedance matching network;

an RF output node in communication with the first and second power transistors through a single output impedance matching network;

a direct-current (DC) collector bias bus line disposed on the RF input side, the DC collector bias bus line connected to a shared collector node of the first and second power transistors; and

a DC base bias bus line connected to respective bases of the first and second power transistors;

wherein the first and second input impedance matching networks are disposed on an RF input side of the amplifier cell.

2. The apparatus of claim 1 , wherein the first and second power transistors are connected in a common emitter configuration.

3. The apparatus of claim 2 , wherein the first input impedance matching network is connected to a base of the first power transistor.

4. The apparatus of claim 3 , wherein the single output impedance matching network is connected to a shared collector node of the first and second power transistors.

5. The apparatus of claim 1 , further comprising:

an RF ground capacitor connected to the shared collector node of the first and second power transistors through at least a portion of the output impedance matching network.

6. The apparatus of claim 1 , wherein the first and second power transistors are identical.

7. An amplifier cell apparatus, comprising:

an RF input node;

first and second impedance circuits in communication with the RF input node, the first and second impedance circuits in communication with first and second power transistors, respectively;

an RF ground capacitor disposed between the first and second impedance circuits; and

a DC base bias bus line connected to respective bases of the first and second power transistors, the DC base bias bus line connected across and separate from at least a portion of the RF output impedance matching network.

8. The apparatus of claim 7 , further comprising:

a direct-current (DC) bias bus disposed across and spaced apart from the first impedance matching network on an input side of the first and second power transistors.

9. The apparatus of claim 8 , further comprising:

an RF output node connected to a shared node of the first and second power transistors through at least a portion of an RF output impedance matching network.

10. The apparatus of claim 9 , wherein the shared node is a shared collector node.

11. The apparatus of claim 9 , wherein the shared node is a shared drain node.

12. An amplifier cell operation method, comprising:

splitting a radio-frequency (RF) input signal for presentation to first and second power transistors through first and second impedance matching networks, respectively;

providing an RF output signal to an RF output node through a single output impedance matching network; and

providing direct-current (DC) collector bias on the RF input side to a shared collector node of the first and second power transistors;

wherein the first and second impedance matching paths are disposed on an RF input side of the first and second power transistors and the RF output node is on an RF output side of the first and second power transistors.

13. An amplifier cell operation method, comprising:

splitting a radio-frequency (RF) input signal for presentation to first and second power transistors through first and second impedance matching networks, respectively;

providing an RF output signal to an RF output node through a single output impedance matching network; and

providing direct-current (DC) drain bias on the RF input side to a shared drain node of the first and second power transistors;

wherein the first and second impedance matching paths are disposed on an RF input side of the first and second power transistors and the RF output node is on an RF output side of the first and second power transistors.

14. The method of claim 13 , further comprising:

providing a DC gate bias to respective gate terminals of the first and second power transistors.