Line-edge roughness improvement for small pitches
View Patent ↗A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.
1. A method of mitigating line-edge roughness in a semiconductor device, the method comprising:
providing a substrate with a plurality of layers formed on the substrate, wherein the plurality of layers comprise: an organic antireflective coating/silicon oxynitride (oARC/SiON) film stack, a high density plasma oxide (HDP) film and a tetraethyl orthosilicate (TEOS) film;
providing a patterned photoresist layer over the plurality of layers formed over the substrate, wherein the patterned photoresist layer is in contact with the oARC/SiON film stack; and
etching the plurality of layers formed on the substrate, using the patterned photoresist layer as an etching mask to form at least one trench in the plurality of layers, wherein a bottom electrode in contact with the semiconductor device has a temperature approximately in a range of 10-15 degrees Celsius during at least the oARC/SiON film etching.
2. The method of mitigating line-edge roughness of claim 1 , wherein the patterned photoresist comprises 193 nanometer (nm) photoresist, for immersion ArF ultra violet lithography, wherein the pattern is formed using 193 nm wavelength radiation.
3. The method of mitigating line-edge roughness of claim 2 , wherein the photoresist is approximately 1150 angstoms (A) thick.
4. The method of mitigating line-edge roughness of claim 1 , wherein an etch bias power for the oARC/SiON film stack etching is approximately 200 watts when an overetch is at least approximately 30 percent.
5. The method of mitigating line-edge roughness of claim 4 , wherein the overetch is less than 30 percent.
6. The method of mitigating line-edge roughness of claim 1 , wherein the plurality of layers further comprises an amorphous carbon film layer, wherein the SiON film layer is removed after the amorphous carbon film etching is complete.
7. The method of mitigating line-edge roughness of claim 1 , wherein a plasma for etching the SiON film layer comprises hydrogen.
8. The method of mitigating line-edge roughness of claim 1 , wherein the etching of the plurality of layers form at least one of a group consisting of vias, trenches, and semiconductor devices.