Apparatuses and methods for setting a signal in variable resistance memory
An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (I READ ) through the STT memory cell and to set a pulse to write the STT memory cell using I READ . Additional embodiments are disclosed.
1. A method, comprising:
reading a variable resistance memory cell; and
writing the memory cell using information obtained in relation to the reading of the memory cell to set a signal to write the memory cell.
2. The method of claim 1 , further comprising determining a reference current, wherein writing the memory cell using information obtained in relation to the reading of the memory cell to set a signal to write the memory cell comprises using the determined reference current to limit the signal.
3. The method of claim 2 , wherein reading the memory cell includes determining a read current (I READ ) flowing through a data line coupled to a spin torque transfer memory cell, wherein determining the reference current includes using the I READ to determine the reference current.
4. The method of claim 3 , further comprising looking up a value from a look-up table, wherein determining the reference current includes summing the I READ and the looked up value to determine the reference current.
5. The method of claim 4 , wherein the looked up value is a function of information that includes at least one type of information selected from the group of information types consisting of:
data to be written into the memory cell;
a temperature;
a process corner;
a power supply voltage; and
a topological location of the memory cell.
6. The method of claim 2 , wherein writing the memory cell includes applying a current ramp up to the reference current.
7. The method of claim 6 , wherein applying the current ramp includes applying a ramp potential on an access line coupled to a gate of an access line transistor, comparing a current flowing through a data line coupled to the cell (I CELL ) to the reference current, and deselecting the data line responsive to the I CELL being equal to or greater than the reference current.
8. The method of claim 7 , wherein comparing the I CELL to the reference current includes using a current mirror to compare the I CELL to the reference current.
9. The method of claim 7 , further comprising compensating the reference current for data line capacitance.
10. The method of claim 9 , further comprising using a dummy data line to compensate the reference current for the data line capacitance.
11. An apparatus, comprising:
a variable resistance memory cell; and
read/write circuitry coupled to the memory cell to determine a read current (I READ ) through the memory cell and to set a pulse to write the memory cell using the I READ .
12. The apparatus of claim 11 , further including an access device, wherein the memory cell includes a magnetic tunnel junction (MTJ) coupled in series with the access device, wherein the access device is configured to control a cell current (I CELL ) through the MTJ.
13. The apparatus of claim 11 , wherein the read/write circuitry is configured to sum the I READ and a ΔI value from a look-up table to provide a reference current, and is configured to set the pulse to write the memory cell using the I SW .