S12 TX FIR architecture
A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
1. A transmitter finite impulse response (TX FIR) architecture, comprising:
a multiplexer;
a plurality of delay cells coupled to the multiplexer;
a plurality of sign operators coupled to the plurality of delay cells;
a plurality of serializer multiplexers, each coupled to a respective sign operator; and
a plurality of driver groups, each coupled to a respective serializer multiplexer.
2. The TX FIR architecture of claim 1 , wherein each driver group comprises at least one driver.
3. The TX FIR architecture of claim 1 , wherein the multiplexer comprises a 20:4 multiplexer configured to output a four-bit data signal.
4. The TX FIR architecture of claim 1 , wherein the multiplexer comprises a 16:4 multiplexer configured to output a four-bit data signal.
5. The TX FIR architecture of claim 1 , wherein the plurality of delay cells are configured to output delayed versions of an input data signal from the multiplexer.
6. The TX FIR architecture of claim 1 , wherein the multiplexer is configured to output a 4-bit data signal; and wherein the plurality of delay cells comprises 6 delay cells configured to output up to six-tap delayed versions of the 4-bit data signal from the multiplexer.
7. The TX FIR architecture of claim 1 , wherein the multiplexer is configured to output a 4-bit data signal; and wherein the plurality of serializer multiplexers each comprises a 4:1 multiplexer configured to serialize the 4-bit data signal into a serial stream.
8. The TX FIR architecture of claim 1 , further comprising a summing unit coupled to the plurality of driver groups.
9. The TX FIR architecture of claim 1 , wherein each driver group comprises at least one driver; and wherein the at least one driver comprises a plurality of binary-weighted differential pairs.
10. The TX FIR architecture of claim 9 , wherein the at least one driver comprises five binary-weighted differential pairs weighted at 1×, 2×, 4×, 8×, and 16×, respectively.
11. The TX FIR architecture of claim 9 , wherein each binary-weighted differential pair is configured to be selectively turned on and off.
12. The TX FIR architecture of claim 1 , wherein each driver group is configured to be selectively turned on and off.
13. The TX FIR architecture of claim 1 , wherein each driver group comprises at least one driver; and wherein each driver is configured to be selectively turned on and off.
14. An electronic device comprising:
a transmitter; and
a finite impulse response equalizer coupled to the transmitter and comprising
a multiplexer,
a plurality of delay cells coupled to the multiplexer,
a plurality of sign operators coupled to the plurality of delay cells,
a plurality of serializer multiplexers, each coupled to a respective sign operator, and
a plurality of driver groups, each coupled to a respective serializer multiplexer.
15. The electronic device of claim 14 , wherein each driver group comprises at least one driver.
16. The electronic device of claim 14 , wherein the plurality of delay cells are configured to output delayed versions of an input data signal from the multiplexer.
17. The electronic device of claim 14 , wherein the multiplexer is configured to output a 4-bit data signal; and wherein the plurality of delay cells comprises 6 delay cells configured to output up to six-tap delayed versions of the 4-bit data signal from the multiplexer.
18. The electronic device of claim 14 , wherein the multiplexer is configured to output a 4-bit data signal; and wherein the plurality of serializer multiplexers each comprises a 4:1 multiplexer configured to serialize the 4-bit data signal into a serial stream.
19. The electronic device of claim 14 , wherein each driver group comprises at least one driver; and wherein the at least one driver comprises a plurality of binary-weighted differential pairs.
20. An electronic device comprising:
a finite impulse response equalizer coupled to the transmitter and comprising
a first multiplexer,
a plurality of delay cells coupled to the first multiplexer,
a plurality of sign operators coupled to the plurality of delay cells,
a plurality of second multiplexers, each coupled to a respective sign operator, and
a plurality of driver groups, each coupled to a respective serializer multiplexer.
21. The electronic device of claim 20 , wherein each driver group comprises at least one driver.
22. The electronic device of claim 20 , wherein the plurality of delay cells are configured to output delayed versions of an input data signal from the first multiplexer.
23. The electronic device of claim 20 , wherein the first multiplexer is configured to output a 4-bit data signal; and wherein the plurality of delay cells comprises 6 delay cells configured to output up to six-tap delayed versions of the 4-bit data signal from the first multiplexer.
24. The electronic device of claim 20 , wherein the first multiplexer is configured to output a 4-bit data signal; and wherein the plurality of second multiplexers each comprises a 4:1 multiplexer configured to serialize the 4-bit data signal into a serial stream.
25. The electronic device of claim 20 , wherein each driver group comprises at least one driver; and wherein the at least one driver comprises a plurality of binary-weighted differential pairs.